tsunami_cchip.hh revision 887
12568SN/A/* 29786Sandreas.hansson@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 38713Sandreas.hansson@arm.com * All rights reserved. 48713Sandreas.hansson@arm.com * 58713Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68713Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78713Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88713Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98713Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108713Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118713Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128713Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138713Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142568SN/A * this software without specific prior written permission. 152568SN/A * 162568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272568SN/A */ 282568SN/A 292568SN/A/* @file 302568SN/A * Emulation of the Tsunami CChip CSRs 312568SN/A */ 322568SN/A 332568SN/A#ifndef __TSUNAMI_CCHIP_HH__ 342568SN/A#define __TSUNAMI_CCHIP_HH__ 352568SN/A 362568SN/A#include "mem/functional_mem/functional_memory.hh" 372568SN/A#include "dev/tsunami.hh" 382568SN/A 392665Ssaidi@eecs.umich.edu/* 402665Ssaidi@eecs.umich.edu * Tsunami CChip 412665Ssaidi@eecs.umich.edu */ 428713Sandreas.hansson@arm.comclass TsunamiCChip : public FunctionalMemory 432568SN/A{ 442568SN/A private: 452568SN/A /** The base address of this device */ 462982Sstever@eecs.umich.edu Addr addr; 4710405Sandreas.hansson@arm.com 488713Sandreas.hansson@arm.com /** The size of mappad from the above address */ 492568SN/A static const Addr size = 0xfff; 502568SN/A 512568SN/A protected: 529164Sandreas.hansson@arm.com /** 532568SN/A * pointer to the tsunami object. 544762Snate@binkert.org * This is our access to all the other tsunami 552568SN/A * devices. 569164Sandreas.hansson@arm.com */ 579164Sandreas.hansson@arm.com Tsunami *tsunami; 588851Sandreas.hansson@arm.com 599180Sandreas.hansson@arm.com /** 609235Sandreas.hansson@arm.com * The dims are device interrupt mask registers. 619164Sandreas.hansson@arm.com * One exists for each CPU, the DRIR X DIM = DIR 629164Sandreas.hansson@arm.com */ 639164Sandreas.hansson@arm.com uint64_t dim[Tsunami::Max_CPUs]; 648851Sandreas.hansson@arm.com 658713Sandreas.hansson@arm.com /** 668713Sandreas.hansson@arm.com * The dirs are device interrupt registers. 678713Sandreas.hansson@arm.com * One exists for each CPU, the DRIR X DIM = DIR 689164Sandreas.hansson@arm.com */ 699164Sandreas.hansson@arm.com uint64_t dir[Tsunami::Max_CPUs]; 708851Sandreas.hansson@arm.com bool dirInterrupting[Tsunami::Max_CPUs]; 719180Sandreas.hansson@arm.com 729164Sandreas.hansson@arm.com /** 739164Sandreas.hansson@arm.com * This register contains bits for each PCI interrupt 742643Sstever@eecs.umich.edu * that can occur. 752643Sstever@eecs.umich.edu */ 762643Sstever@eecs.umich.edu uint64_t drir; 774435Ssaidi@eecs.umich.edu 785034Smilesck@eecs.umich.edu /** 799180Sandreas.hansson@arm.com * The MISC register contains the CPU we are currently on 809180Sandreas.hansson@arm.com * as well as bits to ack RTC and IPI interrupts. 819180Sandreas.hansson@arm.com */ 829180Sandreas.hansson@arm.com uint64_t misc; 832643Sstever@eecs.umich.edu 842643Sstever@eecs.umich.edu /** Count of the number of pending IPIs on a CPU */ 852643Sstever@eecs.umich.edu uint64_t ipiInterrupting[Tsunami::Max_CPUs]; 869294Sandreas.hansson@arm.com 879294Sandreas.hansson@arm.com /** Indicator of which CPUs have had an RTC interrupt */ 888922Swilliam.wang@arm.com bool RTCInterrupting[Tsunami::Max_CPUs]; 898922Swilliam.wang@arm.com 908922Swilliam.wang@arm.com public: 918922Swilliam.wang@arm.com /** 928922Swilliam.wang@arm.com * Initialize the Tsunami CChip by setting all of the 938922Swilliam.wang@arm.com * device register to 0. 948922Swilliam.wang@arm.com * @param name name of this device. 958922Swilliam.wang@arm.com * @param t pointer back to the Tsunami object that we belong to. 969294Sandreas.hansson@arm.com * @param a address we are mapped at. 979294Sandreas.hansson@arm.com * @param mmu pointer to the memory controller that sends us events. 982643Sstever@eecs.umich.edu */ 998713Sandreas.hansson@arm.com TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 1008922Swilliam.wang@arm.com MemoryController *mmu); 1018922Swilliam.wang@arm.com 1028922Swilliam.wang@arm.com /** 1038922Swilliam.wang@arm.com * Process a read to the CChip. 1042643Sstever@eecs.umich.edu * @param req Contains the address to read from. 1052643Sstever@eecs.umich.edu * @param data A pointer to write the read data to. 1062568SN/A * @return The fault condition of the access. 1072568SN/A */ 1082568SN/A virtual Fault read(MemReqPtr &req, uint8_t *data); 1098713Sandreas.hansson@arm.com 1108713Sandreas.hansson@arm.com 11110405Sandreas.hansson@arm.com /** 1124432Ssaidi@eecs.umich.edu * Process a write to the CChip. 1138713Sandreas.hansson@arm.com * @param req Contains the address to write to. 1148713Sandreas.hansson@arm.com * @param data The data to write. 1152568SN/A * @return The fault condition of the access. 1162568SN/A */ 1174433Ssaidi@eecs.umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 1189786Sandreas.hansson@arm.com 1194433Ssaidi@eecs.umich.edu /** 1208713Sandreas.hansson@arm.com * post an RTC interrupt to the CPU 1214435Ssaidi@eecs.umich.edu */ 1224435Ssaidi@eecs.umich.edu void postRTC(); 1234435Ssaidi@eecs.umich.edu 1249786Sandreas.hansson@arm.com /** 1254435Ssaidi@eecs.umich.edu * post an interrupt to the CPU. 1269164Sandreas.hansson@arm.com * @param interrupt the interrupt number to post (0-64) 1274433Ssaidi@eecs.umich.edu */ 1282568SN/A void postDRIR(uint32_t interrupt); 1292568SN/A 1308975Sandreas.hansson@arm.com /** 1312568SN/A * clear an interrupt previously posted to the CPU. 1328713Sandreas.hansson@arm.com * @param interrupt the interrupt number to post (0-64) 1338713Sandreas.hansson@arm.com */ 1349164Sandreas.hansson@arm.com void clearDRIR(uint32_t interrupt); 1358949Sandreas.hansson@arm.com 1362643Sstever@eecs.umich.edu /** 1379164Sandreas.hansson@arm.com * Serialize this object to the given output stream. 1384450Ssaidi@eecs.umich.edu * @param os The stream to serialize to. 1399549Sandreas.hansson@arm.com */ 14010694SMarco.Balboni@ARM.com virtual void serialize(std::ostream &os); 1419549Sandreas.hansson@arm.com 1429180Sandreas.hansson@arm.com /** 1438713Sandreas.hansson@arm.com * Reconstruct the state of this object from a checkpoint. 1448713Sandreas.hansson@arm.com * @param cp The checkpoint use. 1458713Sandreas.hansson@arm.com * @param section The section name of this object 1468713Sandreas.hansson@arm.com */ 1478713Sandreas.hansson@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 1488975Sandreas.hansson@arm.com}; 1498713Sandreas.hansson@arm.com 1509164Sandreas.hansson@arm.com#endif // __TSUNAMI_CCHIP_HH__ 1518949Sandreas.hansson@arm.com