tsunami_cchip.hh revision 4762
1767SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3767SN/A * All rights reserved. 4767SN/A * 5767SN/A * Redistribution and use in source and binary forms, with or without 6767SN/A * modification, are permitted provided that the following conditions are 7767SN/A * met: redistributions of source code must retain the above copyright 8767SN/A * notice, this list of conditions and the following disclaimer; 9767SN/A * redistributions in binary form must reproduce the above copyright 10767SN/A * notice, this list of conditions and the following disclaimer in the 11767SN/A * documentation and/or other materials provided with the distribution; 12767SN/A * neither the name of the copyright holders nor the names of its 13767SN/A * contributors may be used to endorse or promote products derived from 14767SN/A * this software without specific prior written permission. 15767SN/A * 16767SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17767SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18767SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19767SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20767SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21767SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22767SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23767SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24767SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25767SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26767SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 29767SN/A */ 30767SN/A 311722SN/A/** @file 32798SN/A * Emulation of the Tsunami CChip CSRs 33767SN/A */ 34767SN/A 35767SN/A#ifndef __TSUNAMI_CCHIP_HH__ 36767SN/A#define __TSUNAMI_CCHIP_HH__ 37767SN/A 384762Snate@binkert.org#include "base/range.hh" 393540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 40909SN/A#include "dev/io_device.hh" 414762Snate@binkert.org#include "params/TsunamiCChip.hh" 421872SN/A 431722SN/A/** 441722SN/A * Tsunami CChip CSR Emulation. This device includes all the interrupt 451722SN/A * handling code for the chipset. 46767SN/A */ 472523SN/Aclass TsunamiCChip : public BasicPioDevice 48767SN/A{ 49767SN/A protected: 50887SN/A /** 51887SN/A * pointer to the tsunami object. 52887SN/A * This is our access to all the other tsunami 53887SN/A * devices. 54887SN/A */ 55767SN/A Tsunami *tsunami; 56798SN/A 57798SN/A /** 58798SN/A * The dims are device interrupt mask registers. 59798SN/A * One exists for each CPU, the DRIR X DIM = DIR 60798SN/A */ 61767SN/A uint64_t dim[Tsunami::Max_CPUs]; 62798SN/A 63798SN/A /** 64798SN/A * The dirs are device interrupt registers. 65798SN/A * One exists for each CPU, the DRIR X DIM = DIR 66798SN/A */ 67767SN/A uint64_t dir[Tsunami::Max_CPUs]; 68798SN/A 69798SN/A /** 70798SN/A * This register contains bits for each PCI interrupt 71798SN/A * that can occur. 72798SN/A */ 73767SN/A uint64_t drir; 74831SN/A 751290SN/A /** Indicator of which CPUs have an IPI interrupt */ 761290SN/A uint64_t ipint; 77831SN/A 781290SN/A /** Indicator of which CPUs have an RTC interrupt */ 791290SN/A uint64_t itint; 80767SN/A 81767SN/A public: 824762Snate@binkert.org typedef TsunamiCChipParams Params; 83885SN/A /** 84885SN/A * Initialize the Tsunami CChip by setting all of the 85885SN/A * device register to 0. 862523SN/A * @param p params struct 87885SN/A */ 884762Snate@binkert.org TsunamiCChip(const Params *p); 894762Snate@binkert.org 904762Snate@binkert.org const Params * 914762Snate@binkert.org params() const 924762Snate@binkert.org { 934762Snate@binkert.org return dynamic_cast<const Params *>(_params); 944762Snate@binkert.org } 95767SN/A 963349SN/A virtual Tick read(PacketPtr pkt); 97885SN/A 983349SN/A virtual Tick write(PacketPtr pkt); 99767SN/A 100885SN/A /** 101885SN/A * post an RTC interrupt to the CPU 102885SN/A */ 103831SN/A void postRTC(); 104885SN/A 105885SN/A /** 106885SN/A * post an interrupt to the CPU. 107885SN/A * @param interrupt the interrupt number to post (0-64) 108885SN/A */ 109817SN/A void postDRIR(uint32_t interrupt); 110885SN/A 111885SN/A /** 112885SN/A * clear an interrupt previously posted to the CPU. 113885SN/A * @param interrupt the interrupt number to post (0-64) 114885SN/A */ 115817SN/A void clearDRIR(uint32_t interrupt); 116777SN/A 117885SN/A /** 1181290SN/A * post an ipi interrupt to the CPU. 1191290SN/A * @param ipintr the cpu number to clear(bitvector) 1201290SN/A */ 1211290SN/A void clearIPI(uint64_t ipintr); 1221290SN/A 1231290SN/A /** 1241290SN/A * clear a timer interrupt previously posted to the CPU. 1251763SN/A * @param itintr the cpu number to clear(bitvector) 1261290SN/A */ 1271290SN/A void clearITI(uint64_t itintr); 1281290SN/A 1291290SN/A /** 1301290SN/A * request an interrupt be posted to the CPU. 1311290SN/A * @param ipreq the cpu number to interrupt(bitvector) 1321290SN/A */ 1331290SN/A void reqIPI(uint64_t ipreq); 1341290SN/A 1351290SN/A 1361290SN/A /** 137885SN/A * Serialize this object to the given output stream. 138885SN/A * @param os The stream to serialize to. 139885SN/A */ 140767SN/A virtual void serialize(std::ostream &os); 141885SN/A 142885SN/A /** 143885SN/A * Reconstruct the state of this object from a checkpoint. 144885SN/A * @param cp The checkpoint use. 145885SN/A * @param section The section name of this object 146885SN/A */ 147767SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 148909SN/A 149767SN/A}; 150767SN/A 151767SN/A#endif // __TSUNAMI_CCHIP_HH__ 152