tsunami_cchip.hh revision 2665 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Emulation of the Tsunami CChip CSRs
33 */
34
35#ifndef __TSUNAMI_CCHIP_HH__
36#define __TSUNAMI_CCHIP_HH__
37
38#include "dev/tsunami.hh"
39#include "base/range.hh"
40#include "dev/io_device.hh"
41
42
43/**
44 * Tsunami CChip CSR Emulation. This device includes all the interrupt
45 * handling code for the chipset.
46 */
47class TsunamiCChip : public BasicPioDevice
48{
49  protected:
50    /**
51     * pointer to the tsunami object.
52     * This is our access to all the other tsunami
53     * devices.
54     */
55    Tsunami *tsunami;
56
57    /**
58     * The dims are device interrupt mask registers.
59     * One exists for each CPU, the DRIR X DIM = DIR
60     */
61    uint64_t dim[Tsunami::Max_CPUs];
62
63    /**
64     * The dirs are device interrupt registers.
65     * One exists for each CPU, the DRIR X DIM = DIR
66     */
67    uint64_t dir[Tsunami::Max_CPUs];
68
69    /**
70     * This register contains bits for each PCI interrupt
71     * that can occur.
72     */
73    uint64_t drir;
74
75    /** Indicator of which CPUs have an IPI interrupt */
76    uint64_t ipint;
77
78    /** Indicator of which CPUs have an RTC interrupt */
79    uint64_t itint;
80
81  public:
82    struct Params : public BasicPioDevice::Params
83    {
84        Tsunami *tsunami;
85    };
86  protected:
87    const Params *params() const {return (const Params *)_params; }
88
89  public:
90    /**
91     * Initialize the Tsunami CChip by setting all of the
92     * device register to 0.
93     * @param p params struct
94     */
95    TsunamiCChip(Params *p);
96
97    virtual Tick read(Packet *pkt);
98
99    virtual Tick write(Packet *pkt);
100
101    /**
102     * post an RTC interrupt to the CPU
103     */
104    void postRTC();
105
106    /**
107     * post an interrupt to the CPU.
108     * @param interrupt the interrupt number to post (0-64)
109     */
110    void postDRIR(uint32_t interrupt);
111
112    /**
113     * clear an interrupt previously posted to the CPU.
114     * @param interrupt the interrupt number to post (0-64)
115     */
116    void clearDRIR(uint32_t interrupt);
117
118    /**
119     * post an ipi interrupt  to the CPU.
120     * @param ipintr the cpu number to clear(bitvector)
121     */
122    void clearIPI(uint64_t ipintr);
123
124    /**
125     * clear a timer interrupt previously posted to the CPU.
126     * @param itintr the cpu number to clear(bitvector)
127     */
128    void clearITI(uint64_t itintr);
129
130    /**
131     * request an interrupt be posted to the CPU.
132     * @param ipreq the cpu number to interrupt(bitvector)
133     */
134    void reqIPI(uint64_t ipreq);
135
136
137    /**
138     * Serialize this object to the given output stream.
139     * @param os The stream to serialize to.
140     */
141    virtual void serialize(std::ostream &os);
142
143    /**
144     * Reconstruct the state of this object from a checkpoint.
145     * @param cp The checkpoint use.
146     * @param section The section name of this object
147     */
148    virtual void unserialize(Checkpoint *cp, const std::string &section);
149
150};
151
152#endif // __TSUNAMI_CCHIP_HH__
153