tsunami_cchip.hh revision 2523
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 310717Sandreas.hansson@arm.com * All rights reserved. 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 67404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147404SAli.Saidi@ARM.com * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu */ 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.edu/** @file 306019Shines@cs.fsu.edu * Emulation of the Tsunami CChip CSRs 316019Shines@cs.fsu.edu */ 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu#ifndef __TSUNAMI_CCHIP_HH__ 346019Shines@cs.fsu.edu#define __TSUNAMI_CCHIP_HH__ 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edu#include "dev/tsunami.hh" 376019Shines@cs.fsu.edu#include "base/range.hh" 387404SAli.Saidi@ARM.com#include "dev/io_device.hh" 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.edu 416019Shines@cs.fsu.edu/** 427404SAli.Saidi@ARM.com * Tsunami CChip CSR Emulation. This device includes all the interrupt 4313665Sandreas.sandberg@arm.com * handling code for the chipset. 4413892Sgabeblack@google.com */ 457404SAli.Saidi@ARM.comclass TsunamiCChip : public BasicPioDevice 4610037SARM gem5 Developers{ 4713892Sgabeblack@google.com protected: 488756Sgblack@eecs.umich.edu /** 498756Sgblack@eecs.umich.edu * pointer to the tsunami object. 509338SAndreas.Sandberg@arm.com * This is our access to all the other tsunami 5110037SARM gem5 Developers * devices. 529258SAli.Saidi@ARM.com */ 539258SAli.Saidi@ARM.com Tsunami *tsunami; 546019Shines@cs.fsu.edu 5510717Sandreas.hansson@arm.com /** 5610717Sandreas.hansson@arm.com * The dims are device interrupt mask registers. 5710717Sandreas.hansson@arm.com * One exists for each CPU, the DRIR X DIM = DIR 5810717Sandreas.hansson@arm.com */ 5910717Sandreas.hansson@arm.com uint64_t dim[Tsunami::Max_CPUs]; 6010717Sandreas.hansson@arm.com 6110717Sandreas.hansson@arm.com /** 6210717Sandreas.hansson@arm.com * The dirs are device interrupt registers. 6312433Sgabeblack@google.com * One exists for each CPU, the DRIR X DIM = DIR 646019Shines@cs.fsu.edu */ 656020Sgblack@eecs.umich.edu uint64_t dir[Tsunami::Max_CPUs]; 669338SAndreas.Sandberg@arm.com 6712005Sandreas.sandberg@arm.com /** 686116Snate@binkert.org * This register contains bits for each PCI interrupt 698756Sgblack@eecs.umich.edu * that can occur. 7010037SARM gem5 Developers */ 7110037SARM gem5 Developers uint64_t drir; 7210037SARM gem5 Developers 7310037SARM gem5 Developers /** Indicator of which CPUs have an IPI interrupt */ 7410037SARM gem5 Developers uint64_t ipint; 7510037SARM gem5 Developers 7610037SARM gem5 Developers /** Indicator of which CPUs have an RTC interrupt */ 7710037SARM gem5 Developers uint64_t itint; 7810037SARM gem5 Developers 7910037SARM gem5 Developers public: 8010037SARM gem5 Developers struct Params : public BasicPioDevice::Params 8110037SARM gem5 Developers { 8210037SARM gem5 Developers Tsunami *tsunami; 8310037SARM gem5 Developers }; 8410037SARM gem5 Developers protected: 8510037SARM gem5 Developers const Params *params() const {return (const Params *)_params; } 8610037SARM gem5 Developers 8710037SARM gem5 Developers public: 8810717Sandreas.hansson@arm.com /** 8910717Sandreas.hansson@arm.com * Initialize the Tsunami CChip by setting all of the 9010037SARM gem5 Developers * device register to 0. 9110717Sandreas.hansson@arm.com * @param p params struct 9210717Sandreas.hansson@arm.com */ 9310037SARM gem5 Developers TsunamiCChip(Params *p); 9410717Sandreas.hansson@arm.com 9510037SARM gem5 Developers virtual Tick read(Packet &pkt); 9610037SARM gem5 Developers 9710717Sandreas.hansson@arm.com virtual Tick write(Packet &pkt); 9810717Sandreas.hansson@arm.com 9910037SARM gem5 Developers /** 10010717Sandreas.hansson@arm.com * post an RTC interrupt to the CPU 101 */ 102 void postRTC(); 103 104 /** 105 * post an interrupt to the CPU. 106 * @param interrupt the interrupt number to post (0-64) 107 */ 108 void postDRIR(uint32_t interrupt); 109 110 /** 111 * clear an interrupt previously posted to the CPU. 112 * @param interrupt the interrupt number to post (0-64) 113 */ 114 void clearDRIR(uint32_t interrupt); 115 116 /** 117 * post an ipi interrupt to the CPU. 118 * @param ipintr the cpu number to clear(bitvector) 119 */ 120 void clearIPI(uint64_t ipintr); 121 122 /** 123 * clear a timer interrupt previously posted to the CPU. 124 * @param itintr the cpu number to clear(bitvector) 125 */ 126 void clearITI(uint64_t itintr); 127 128 /** 129 * request an interrupt be posted to the CPU. 130 * @param ipreq the cpu number to interrupt(bitvector) 131 */ 132 void reqIPI(uint64_t ipreq); 133 134 135 /** 136 * Serialize this object to the given output stream. 137 * @param os The stream to serialize to. 138 */ 139 virtual void serialize(std::ostream &os); 140 141 /** 142 * Reconstruct the state of this object from a checkpoint. 143 * @param cp The checkpoint use. 144 * @param section The section name of this object 145 */ 146 virtual void unserialize(Checkpoint *cp, const std::string §ion); 147 148}; 149 150#endif // __TSUNAMI_CCHIP_HH__ 151