tsunami_cchip.hh revision 1762
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2004-2005 The Regents of The University of Michigan 37399SAli.Saidi@ARM.com * All rights reserved. 47399SAli.Saidi@ARM.com * 57399SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67399SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77399SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97399SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117399SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127399SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137399SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu */ 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.edu/** @file 306019Shines@cs.fsu.edu * Emulation of the Tsunami CChip CSRs 316019Shines@cs.fsu.edu */ 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu#ifndef __TSUNAMI_CCHIP_HH__ 346019Shines@cs.fsu.edu#define __TSUNAMI_CCHIP_HH__ 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edu#include "dev/tsunami.hh" 376019Shines@cs.fsu.edu#include "base/range.hh" 386019Shines@cs.fsu.edu#include "dev/io_device.hh" 396019Shines@cs.fsu.edu 407399SAli.Saidi@ARM.com/** 416019Shines@cs.fsu.edu * Tsunami CChip CSR Emulation. This device includes all the interrupt 426019Shines@cs.fsu.edu * handling code for the chipset. 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.educlass TsunamiCChip : public PioDevice 456019Shines@cs.fsu.edu{ 466019Shines@cs.fsu.edu private: 476019Shines@cs.fsu.edu /** The base address of this device */ 488229Snate@binkert.org Addr addr; 496019Shines@cs.fsu.edu 506019Shines@cs.fsu.edu /** The size of mappad from the above address */ 516019Shines@cs.fsu.edu static const Addr size = 0xfffffff; 5210037SARM gem5 Developers 536019Shines@cs.fsu.edu protected: 546116Snate@binkert.org /** 557878Sgblack@eecs.umich.edu * pointer to the tsunami object. 5610463SAndreas.Sandberg@ARM.com * This is our access to all the other tsunami 576019Shines@cs.fsu.edu * devices. 586019Shines@cs.fsu.edu */ 596019Shines@cs.fsu.edu Tsunami *tsunami; 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.edu /** 626019Shines@cs.fsu.edu * The dims are device interrupt mask registers. 637404SAli.Saidi@ARM.com * One exists for each CPU, the DRIR X DIM = DIR 6410037SARM gem5 Developers */ 6510037SARM gem5 Developers uint64_t dim[Tsunami::Max_CPUs]; 667404SAli.Saidi@ARM.com 676019Shines@cs.fsu.edu /** 686019Shines@cs.fsu.edu * The dirs are device interrupt registers. 697294Sgblack@eecs.umich.edu * One exists for each CPU, the DRIR X DIM = DIR 707294Sgblack@eecs.umich.edu */ 7110037SARM gem5 Developers uint64_t dir[Tsunami::Max_CPUs]; 727294Sgblack@eecs.umich.edu 737294Sgblack@eecs.umich.edu /** 747294Sgblack@eecs.umich.edu * This register contains bits for each PCI interrupt 7510037SARM gem5 Developers * that can occur. 7610037SARM gem5 Developers */ 7710037SARM gem5 Developers uint64_t drir; 7810037SARM gem5 Developers 797294Sgblack@eecs.umich.edu /** Indicator of which CPUs have an IPI interrupt */ 8010037SARM gem5 Developers uint64_t ipint; 817404SAli.Saidi@ARM.com 8210037SARM gem5 Developers /** Indicator of which CPUs have an RTC interrupt */ 837294Sgblack@eecs.umich.edu uint64_t itint; 847294Sgblack@eecs.umich.edu 857294Sgblack@eecs.umich.edu public: 8610037SARM gem5 Developers /** 8710037SARM gem5 Developers * Initialize the Tsunami CChip by setting all of the 8810037SARM gem5 Developers * device register to 0. 8910037SARM gem5 Developers * @param name name of this device. 9010037SARM gem5 Developers * @param t pointer back to the Tsunami object that we belong to. 9110037SARM gem5 Developers * @param a address we are mapped at. 9210037SARM gem5 Developers * @param mmu pointer to the memory controller that sends us events. 9310037SARM gem5 Developers * @param hier object to store parameters universal the device hierarchy 9410037SARM gem5 Developers * @param bus The bus that this device is attached to 9510037SARM gem5 Developers */ 967294Sgblack@eecs.umich.edu TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 976019Shines@cs.fsu.edu MemoryController *mmu, HierParams *hier, Bus *bus, 9810037SARM gem5 Developers Tick pio_latency); 9910037SARM gem5 Developers 10010037SARM gem5 Developers /** 10110037SARM gem5 Developers * Process a read to the CChip. 10210037SARM gem5 Developers * @param req Contains the address to read from. 10310037SARM gem5 Developers * @param data A pointer to write the read data to. 10410037SARM gem5 Developers * @return The fault condition of the access. 1057436Sdam.sunwoo@arm.com */ 1067404SAli.Saidi@ARM.com virtual Fault read(MemReqPtr &req, uint8_t *data); 10710037SARM gem5 Developers 10810037SARM gem5 Developers 1096019Shines@cs.fsu.edu /** 1107399SAli.Saidi@ARM.com * Process a write to the CChip. 1117734SAli.Saidi@ARM.com * @param req Contains the address to write to. 1127734SAli.Saidi@ARM.com * @param data The data to write. 1137734SAli.Saidi@ARM.com * @return The fault condition of the access. 1147734SAli.Saidi@ARM.com */ 1157734SAli.Saidi@ARM.com virtual Fault write(MemReqPtr &req, const uint8_t *data); 1167734SAli.Saidi@ARM.com 1177734SAli.Saidi@ARM.com /** 1187734SAli.Saidi@ARM.com * post an RTC interrupt to the CPU 1197734SAli.Saidi@ARM.com */ 1207734SAli.Saidi@ARM.com void postRTC(); 1217734SAli.Saidi@ARM.com 1227734SAli.Saidi@ARM.com /** 1237734SAli.Saidi@ARM.com * post an interrupt to the CPU. 1247734SAli.Saidi@ARM.com * @param interrupt the interrupt number to post (0-64) 1257734SAli.Saidi@ARM.com */ 1267734SAli.Saidi@ARM.com void postDRIR(uint32_t interrupt); 1277734SAli.Saidi@ARM.com 1287734SAli.Saidi@ARM.com /** 1297734SAli.Saidi@ARM.com * clear an interrupt previously posted to the CPU. 1307734SAli.Saidi@ARM.com * @param interrupt the interrupt number to post (0-64) 1316019Shines@cs.fsu.edu */ 1326019Shines@cs.fsu.edu void clearDRIR(uint32_t interrupt); 1336019Shines@cs.fsu.edu 1346019Shines@cs.fsu.edu /** 13510463SAndreas.Sandberg@ARM.com * post an ipi interrupt to the CPU. 13610463SAndreas.Sandberg@ARM.com * @param ipintr the cpu number to clear(bitvector) 13710463SAndreas.Sandberg@ARM.com */ 1387697SAli.Saidi@ARM.com void clearIPI(uint64_t ipintr); 1397404SAli.Saidi@ARM.com 1408527SAli.Saidi@ARM.com /** 1418527SAli.Saidi@ARM.com * clear a timer interrupt previously posted to the CPU. 1426019Shines@cs.fsu.edu * @param interrupt the cpu number to clear(bitvector) 14310037SARM gem5 Developers */ 14410037SARM gem5 Developers void clearITI(uint64_t itintr); 1456019Shines@cs.fsu.edu 1469535Smrinmoy.ghosh@arm.com /** 1479535Smrinmoy.ghosh@arm.com * request an interrupt be posted to the CPU. 1489535Smrinmoy.ghosh@arm.com * @param ipreq the cpu number to interrupt(bitvector) 14910037SARM gem5 Developers */ 15010037SARM gem5 Developers void reqIPI(uint64_t ipreq); 15110037SARM gem5 Developers 1529535Smrinmoy.ghosh@arm.com 15310037SARM gem5 Developers /** 15410037SARM gem5 Developers * Serialize this object to the given output stream. 1559535Smrinmoy.ghosh@arm.com * @param os The stream to serialize to. 15610037SARM gem5 Developers */ 15710037SARM gem5 Developers virtual void serialize(std::ostream &os); 15810037SARM gem5 Developers 1599535Smrinmoy.ghosh@arm.com /** 1606019Shines@cs.fsu.edu * Reconstruct the state of this object from a checkpoint. 16110037SARM gem5 Developers * @param cp The checkpoint use. 16210194SGeoffrey.Blake@arm.com * @param section The section name of this object 16310194SGeoffrey.Blake@arm.com */ 16410037SARM gem5 Developers virtual void unserialize(Checkpoint *cp, const std::string §ion); 16510037SARM gem5 Developers 16610037SARM gem5 Developers /** 16710037SARM gem5 Developers * Return how long this access will take. 16810037SARM gem5 Developers * @param req the memory request to calcuate 1696019Shines@cs.fsu.edu * @return Tick when the request is done 1706019Shines@cs.fsu.edu */ 1717404SAli.Saidi@ARM.com Tick cacheAccess(MemReqPtr &req); 1727404SAli.Saidi@ARM.com}; 17310037SARM gem5 Developers 17410037SARM gem5 Developers#endif // __TSUNAMI_CCHIP_HH__ 17510037SARM gem5 Developers