tsunami.hh revision 1113
12SN/A/* 21762SN/A * Copyright (c) 2004 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu/** 302665Ssaidi@eecs.umich.edu * @file 312SN/A * Declaration of top level class for the Tsunami chipset. This class just 322SN/A * retains pointers to all its children so the children can communicate. 332SN/A */ 342SN/A 352SN/A#ifndef __TSUNAMI_HH__ 362655Sstever@eecs.umich.edu#define __TSUNAMI_HH__ 372655Sstever@eecs.umich.edu 382SN/A#include "dev/platform.hh" 392SN/A 401399SN/Aclass IdeController; 411396SN/Aclass TlaserClock; 422SN/Aclass NSGigE; 432SN/Aclass TsunamiCChip; 442729Ssaidi@eecs.umich.educlass TsunamiPChip; 452SN/Aclass TsunamiIO; 461310SN/Aclass PciConfigAll; 472SN/Aclass System; 482SN/A 492SN/A/** 502667Sstever@eecs.umich.edu * Top level class for Tsunami Chipset emulation. 5156SN/A * This structure just contains pointers to all the 52146SN/A * children so the children can commnicate to do the 531388SN/A * read work 5456SN/A */ 5556SN/A 561311SN/Aclass Tsunami : public Platform 57400SN/A{ 581717SN/A public: 591717SN/A 60146SN/A /** Max number of CPUs in a Tsunami */ 61146SN/A static const int Max_CPUs = 4; 62146SN/A 63146SN/A /** Pointer to the system */ 6456SN/A System *system; 6556SN/A 6656SN/A /** Pointer to the TsunamiIO device which has the RTC */ 67695SN/A TsunamiIO *io; 68695SN/A 691696SN/A /** Pointer to the Tsunami CChip. 702SN/A * The chip contains some configuration information and 712SN/A * all the interrupt mask and status registers 722SN/A */ 732SN/A TsunamiCChip *cchip; 742SN/A 752SN/A /** Pointer to the Tsunami PChip. 76329SN/A * The pchip is the interface to the PCI bus, in our case 772SN/A * it does not have to do much. 782SN/A */ 792SN/A TsunamiPChip *pchip; 802SN/A 812SN/A int intr_sum_type[Tsunami::Max_CPUs]; 822SN/A int ipi_pending[Tsunami::Max_CPUs]; 832SN/A 842SN/A public: 852SN/A /** 862SN/A * Constructor for the Tsunami Class. 872SN/A * @param name name of the object 882SN/A * @param con pointer to the console 89329SN/A * @param intrcontrol pointer to the interrupt controller 90329SN/A * @param intrFreq frequency that interrupts happen 91329SN/A */ 92329SN/A Tsunami(const std::string &name, System *s, IntrControl *intctrl, 93329SN/A PciConfigAll *pci, int intrFreq); 94329SN/A 95329SN/A /** 962SN/A * Return the interrupting frequency to AlphaAccess 972SN/A * @return frequency of RTC interrupts 982SN/A */ 992SN/A virtual Tick intrFrequency(); 1002SN/A 1012SN/A /** 1022SN/A * Cause the cpu to post a serial interrupt to the CPU. 1032SN/A */ 104764SN/A virtual void postConsoleInt(); 105764SN/A 106764SN/A /** 107764SN/A * Clear a posted CPU interrupt (id=55) 108764SN/A */ 109764SN/A virtual void clearConsoleInt(); 110764SN/A 111764SN/A /** 112764SN/A * Serialize this object to the given output stream. 113764SN/A * @param os The stream to serialize to. 114764SN/A */ 115764SN/A virtual void serialize(std::ostream &os); 1162729Ssaidi@eecs.umich.edu 1172729Ssaidi@eecs.umich.edu /** 1182729Ssaidi@eecs.umich.edu * Reconstruct the state of this object from a checkpoint. 1192729Ssaidi@eecs.umich.edu * @param cp The checkpoint use. 1202729Ssaidi@eecs.umich.edu * @param section The section name of this object 1212729Ssaidi@eecs.umich.edu */ 1222729Ssaidi@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1232729Ssaidi@eecs.umich.edu}; 1242729Ssaidi@eecs.umich.edu 1252729Ssaidi@eecs.umich.edu#endif // __TSUNAMI_HH__ 1262729Ssaidi@eecs.umich.edu