tsunami.hh revision 5034
1767SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3767SN/A * All rights reserved.
4767SN/A *
5767SN/A * Redistribution and use in source and binary forms, with or without
6767SN/A * modification, are permitted provided that the following conditions are
7767SN/A * met: redistributions of source code must retain the above copyright
8767SN/A * notice, this list of conditions and the following disclaimer;
9767SN/A * redistributions in binary form must reproduce the above copyright
10767SN/A * notice, this list of conditions and the following disclaimer in the
11767SN/A * documentation and/or other materials provided with the distribution;
12767SN/A * neither the name of the copyright holders nor the names of its
13767SN/A * contributors may be used to endorse or promote products derived from
14767SN/A * this software without specific prior written permission.
15767SN/A *
16767SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17767SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18767SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19767SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20767SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21767SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22767SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23767SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24767SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25767SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26767SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
29767SN/A */
30767SN/A
31779SN/A/**
32779SN/A * @file
33798SN/A * Declaration of top level class for the Tsunami chipset. This class just
34798SN/A * retains pointers to all its children so the children can communicate.
35779SN/A */
36779SN/A
371401SN/A#ifndef __DEV_TSUNAMI_HH__
381401SN/A#define __DEV_TSUNAMI_HH__
39767SN/A
40806SN/A#include "dev/platform.hh"
415034Smilesck@eecs.umich.edu#include "params/Tsunami.hh"
42767SN/A
43848SN/Aclass IdeController;
44767SN/Aclass TsunamiCChip;
45768SN/Aclass TsunamiPChip;
46806SN/Aclass TsunamiIO;
47806SN/Aclass System;
48779SN/A
49779SN/A/**
50779SN/A  * Top level class for Tsunami Chipset emulation.
51779SN/A  * This structure just contains pointers to all the
52779SN/A  * children so the children can commnicate to do the
53779SN/A  * read work
54779SN/A  */
55767SN/A
56806SN/Aclass Tsunami : public Platform
57767SN/A{
58767SN/A  public:
59779SN/A    /** Max number of CPUs in a Tsunami */
601290SN/A    static const int Max_CPUs = 64;
61767SN/A
62806SN/A    /** Pointer to the system */
63806SN/A    System *system;
641113SN/A
65806SN/A    /** Pointer to the TsunamiIO device which has the RTC */
66806SN/A    TsunamiIO *io;
67767SN/A
68779SN/A    /** Pointer to the Tsunami CChip.
691401SN/A     * The chip contains some configuration information and
701401SN/A     * all the interrupt mask and status registers
711401SN/A     */
72767SN/A    TsunamiCChip *cchip;
73779SN/A
74779SN/A    /** Pointer to the Tsunami PChip.
751401SN/A     * The pchip is the interface to the PCI bus, in our case
761401SN/A     * it does not have to do much.
771401SN/A     */
78768SN/A    TsunamiPChip *pchip;
79767SN/A
80767SN/A    int intr_sum_type[Tsunami::Max_CPUs];
81767SN/A    int ipi_pending[Tsunami::Max_CPUs];
82767SN/A
83767SN/A  public:
845034Smilesck@eecs.umich.edu    typedef TsunamiParams Params;
855034Smilesck@eecs.umich.edu    Tsunami(const Params *p);
86865SN/A
87885SN/A    /**
88891SN/A     * Return the interrupting frequency to AlphaAccess
89891SN/A     * @return frequency of RTC interrupts
90891SN/A     */
911401SN/A    virtual Tick intrFrequency();
92891SN/A
93891SN/A    /**
94885SN/A     * Cause the cpu to post a serial interrupt to the CPU.
95885SN/A     */
96865SN/A    virtual void postConsoleInt();
97885SN/A
98885SN/A    /**
99885SN/A     * Clear a posted CPU interrupt (id=55)
100885SN/A     */
101865SN/A    virtual void clearConsoleInt();
102767SN/A
103885SN/A    /**
1041095SN/A     * Cause the chipset to post a cpi interrupt to the CPU.
1051095SN/A     */
1061095SN/A    virtual void postPciInt(int line);
1071095SN/A
1081095SN/A    /**
1091095SN/A     * Clear a posted PCI->CPU interrupt
1101095SN/A     */
1111095SN/A    virtual void clearPciInt(int line);
1121095SN/A
1132846SN/A
1141149SN/A    virtual Addr pciToDma(Addr pciAddr) const;
1151149SN/A
1161401SN/A    /**
1172846SN/A     * Calculate the configuration address given a bus/dev/func.
1182846SN/A     */
1192846SN/A    virtual Addr calcConfigAddr(int bus, int dev, int func);
1202846SN/A
1212846SN/A    /**
122885SN/A     * Serialize this object to the given output stream.
123885SN/A     * @param os The stream to serialize to.
124885SN/A     */
125767SN/A    virtual void serialize(std::ostream &os);
126885SN/A
127885SN/A    /**
128885SN/A     * Reconstruct the state of this object from a checkpoint.
129885SN/A     * @param cp The checkpoint use.
130885SN/A     * @param section The section name of this object
131885SN/A     */
132767SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
133767SN/A};
134767SN/A
1351401SN/A#endif // __DEV_TSUNAMI_HH__
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