tsunami.hh revision 1401 
1/*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @file
31 * Declaration of top level class for the Tsunami chipset. This class just
32 * retains pointers to all its children so the children can communicate.
33 */
34
35#ifndef __DEV_TSUNAMI_HH__
36#define __DEV_TSUNAMI_HH__
37
38#include "dev/platform.hh"
39
40class IdeController;
41class TlaserClock;
42class NSGigE;
43class TsunamiCChip;
44class TsunamiPChip;
45class TsunamiIO;
46class PciConfigAll;
47class System;
48
49/**
50  * Top level class for Tsunami Chipset emulation.
51  * This structure just contains pointers to all the
52  * children so the children can commnicate to do the
53  * read work
54  */
55
56class Tsunami : public Platform
57{
58  public:
59    /** Max number of CPUs in a Tsunami */
60    static const int Max_CPUs = 64;
61
62    /** Pointer to the system */
63    System *system;
64
65    /** Pointer to the TsunamiIO device which has the RTC */
66    TsunamiIO *io;
67
68    /** Pointer to the Tsunami CChip.
69     * The chip contains some configuration information and
70     * all the interrupt mask and status registers
71     */
72    TsunamiCChip *cchip;
73
74    /** Pointer to the Tsunami PChip.
75     * The pchip is the interface to the PCI bus, in our case
76     * it does not have to do much.
77     */
78    TsunamiPChip *pchip;
79
80    int intr_sum_type[Tsunami::Max_CPUs];
81    int ipi_pending[Tsunami::Max_CPUs];
82
83  public:
84    /**
85     * Constructor for the Tsunami Class.
86     * @param name name of the object
87     * @param con pointer to the console
88     * @param intrcontrol pointer to the interrupt controller
89     * @param intrFreq frequency that interrupts happen
90     */
91    Tsunami(const std::string &name, System *s, IntrControl *intctrl,
92            PciConfigAll *pci, int intrFreq);
93
94    /**
95     * Return the interrupting frequency to AlphaAccess
96     * @return frequency of RTC interrupts
97     */
98    virtual Tick intrFrequency();
99
100    /**
101     * Cause the cpu to post a serial interrupt to the CPU.
102     */
103    virtual void postConsoleInt();
104
105    /**
106     * Clear a posted CPU interrupt (id=55)
107     */
108    virtual void clearConsoleInt();
109
110    /**
111     * Cause the chipset to post a cpi interrupt to the CPU.
112     */
113    virtual void postPciInt(int line);
114
115    /**
116     * Clear a posted PCI->CPU interrupt
117     */
118    virtual void clearPciInt(int line);
119
120    virtual Addr pciToDma(Addr pciAddr) const;
121
122    /**
123     * Serialize this object to the given output stream.
124     * @param os The stream to serialize to.
125     */
126    virtual void serialize(std::ostream &os);
127
128    /**
129     * Reconstruct the state of this object from a checkpoint.
130     * @param cp The checkpoint use.
131     * @param section The section name of this object
132     */
133    virtual void unserialize(Checkpoint *cp, const std::string &section);
134};
135
136#endif // __DEV_TSUNAMI_HH__
137