tsunami.cc revision 10905
1767SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3767SN/A * All rights reserved.
4767SN/A *
5767SN/A * Redistribution and use in source and binary forms, with or without
6767SN/A * modification, are permitted provided that the following conditions are
7767SN/A * met: redistributions of source code must retain the above copyright
8767SN/A * notice, this list of conditions and the following disclaimer;
9767SN/A * redistributions in binary form must reproduce the above copyright
10767SN/A * notice, this list of conditions and the following disclaimer in the
11767SN/A * documentation and/or other materials provided with the distribution;
12767SN/A * neither the name of the copyright holders nor the names of its
13767SN/A * contributors may be used to endorse or promote products derived from
14767SN/A * this software without specific prior written permission.
15767SN/A *
16767SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17767SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18767SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19767SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20767SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21767SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22767SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23767SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24767SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25767SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26767SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
29767SN/A */
30767SN/A
311763SN/A/** @file
321763SN/A * Implementation of Tsunami platform.
331730SN/A */
341730SN/A
35767SN/A#include <deque>
36767SN/A#include <string>
37767SN/A#include <vector>
38767SN/A
398741Sgblack@eecs.umich.edu#include "arch/alpha/system.hh"
406658Snate@binkert.org#include "config/the_isa.hh"
41767SN/A#include "cpu/intr_control.hh"
428229Snate@binkert.org#include "dev/alpha/tsunami.hh"
433540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh"
448229Snate@binkert.org#include "dev/alpha/tsunami_io.hh"
453540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_pchip.hh"
465478Snate@binkert.org#include "dev/terminal.hh"
47767SN/A
48767SN/Ausing namespace std;
492107SN/A//Should this be AlphaISA?
502107SN/Ausing namespace TheISA;
51767SN/A
525034Smilesck@eecs.umich.eduTsunami::Tsunami(const Params *p)
535034Smilesck@eecs.umich.edu    : Platform(p), system(p->system)
54767SN/A{
55767SN/A    for (int i = 0; i < Tsunami::Max_CPUs; i++)
56767SN/A        intr_sum_type[i] = 0;
57767SN/A}
58767SN/A
598741Sgblack@eecs.umich.eduvoid
608741Sgblack@eecs.umich.eduTsunami::init()
61891SN/A{
628741Sgblack@eecs.umich.edu    AlphaSystem *alphaSystem = dynamic_cast<AlphaSystem *>(system);
638741Sgblack@eecs.umich.edu    assert(alphaSystem);
648741Sgblack@eecs.umich.edu    alphaSystem->setIntrFreq(io->frequency());
65891SN/A}
66891SN/A
67767SN/Avoid
68865SN/ATsunami::postConsoleInt()
69865SN/A{
70865SN/A    io->postPIC(0x10);
71865SN/A}
72865SN/A
73865SN/Avoid
74865SN/ATsunami::clearConsoleInt()
75865SN/A{
76865SN/A    io->clearPIC(0x10);
77865SN/A}
78865SN/A
79865SN/Avoid
801095SN/ATsunami::postPciInt(int line)
811095SN/A{
821599SN/A    cchip->postDRIR(line);
831095SN/A}
841095SN/A
851095SN/Avoid
861095SN/ATsunami::clearPciInt(int line)
871095SN/A{
881599SN/A    cchip->clearDRIR(line);
891149SN/A}
901149SN/A
911149SN/AAddr
921149SN/ATsunami::pciToDma(Addr pciAddr) const
931149SN/A{
941149SN/A    return pchip->translatePciToDma(pciAddr);
951095SN/A}
961095SN/A
972846SN/A
982846SN/AAddr
995834Sgblack@eecs.umich.eduTsunami::calcPciConfigAddr(int bus, int dev, int func)
1002846SN/A{
1012846SN/A   return pchip->calcConfigAddr(bus, dev, func);
1022846SN/A}
1032846SN/A
1045834Sgblack@eecs.umich.eduAddr
1055834Sgblack@eecs.umich.eduTsunami::calcPciIOAddr(Addr addr)
1065834Sgblack@eecs.umich.edu{
1075834Sgblack@eecs.umich.edu   return pchip->calcIOAddr(addr);
1085834Sgblack@eecs.umich.edu}
1095834Sgblack@eecs.umich.edu
1105834Sgblack@eecs.umich.eduAddr
1115834Sgblack@eecs.umich.eduTsunami::calcPciMemAddr(Addr addr)
1125834Sgblack@eecs.umich.edu{
1135834Sgblack@eecs.umich.edu   return pchip->calcMemAddr(addr);
1145834Sgblack@eecs.umich.edu}
1155834Sgblack@eecs.umich.edu
1161095SN/Avoid
11710905Sandreas.sandberg@arm.comTsunami::serialize(CheckpointOut &cp) const
118767SN/A{
119767SN/A    SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
120767SN/A}
121767SN/A
122767SN/Avoid
12310905Sandreas.sandberg@arm.comTsunami::unserialize(CheckpointIn &cp)
124767SN/A{
125767SN/A    UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
126767SN/A}
127767SN/A
1284762Snate@binkert.orgTsunami *
1294762Snate@binkert.orgTsunamiParams::create()
130767SN/A{
1315034Smilesck@eecs.umich.edu    return new Tsunami(this);
132767SN/A}
133