tsunami.cc revision 10905
11897Sstever@eecs.umich.edu/* 24130Ssaidi@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 31897Sstever@eecs.umich.edu * All rights reserved. 41897Sstever@eecs.umich.edu * 51897Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 61897Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 71897Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 81897Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 91897Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 101897Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 111897Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 121897Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 131897Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 141897Sstever@eecs.umich.edu * this software without specific prior written permission. 151897Sstever@eecs.umich.edu * 161897Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171897Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181897Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191897Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201897Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211897Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221897Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231897Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241897Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251897Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261897Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271897Sstever@eecs.umich.edu * 281897Sstever@eecs.umich.edu * Authors: Ali Saidi 291897Sstever@eecs.umich.edu */ 301897Sstever@eecs.umich.edu 311897Sstever@eecs.umich.edu/** @file 321897Sstever@eecs.umich.edu * Implementation of Tsunami platform. 331897Sstever@eecs.umich.edu */ 344961Ssaidi@eecs.umich.edu 351897Sstever@eecs.umich.edu#include <deque> 361897Sstever@eecs.umich.edu#include <string> 371897Sstever@eecs.umich.edu#include <vector> 381897Sstever@eecs.umich.edu 397047Snate@binkert.org#include "arch/alpha/system.hh" 408319Ssteve.reinhardt@amd.com#include "config/the_isa.hh" 417047Snate@binkert.org#include "cpu/intr_control.hh" 428319Ssteve.reinhardt@amd.com#include "dev/alpha/tsunami.hh" 4311706Sandreas.hansson@arm.com#include "dev/alpha/tsunami_cchip.hh" 448811Sandreas.hansson@arm.com#include "dev/alpha/tsunami_io.hh" 459850Sandreas.hansson@arm.com#include "dev/alpha/tsunami_pchip.hh" 4611706Sandreas.hansson@arm.com#include "dev/terminal.hh" 4711706Sandreas.hansson@arm.com 4811706Sandreas.hansson@arm.comusing namespace std; 4911706Sandreas.hansson@arm.com//Should this be AlphaISA? 508811Sandreas.hansson@arm.comusing namespace TheISA; 518811Sandreas.hansson@arm.com 5210007Snilay@cs.wisc.eduTsunami::Tsunami(const Params *p) 5311308Santhony.gutierrez@amd.com : Platform(p), system(p->system) 5411308Santhony.gutierrez@amd.com{ 557047Snate@binkert.org for (int i = 0; i < Tsunami::Max_CPUs; i++) 568811Sandreas.hansson@arm.com intr_sum_type[i] = 0; 578811Sandreas.hansson@arm.com} 588811Sandreas.hansson@arm.com 598319Ssteve.reinhardt@amd.comvoid 608319Ssteve.reinhardt@amd.comTsunami::init() 618319Ssteve.reinhardt@amd.com{ 628319Ssteve.reinhardt@amd.com AlphaSystem *alphaSystem = dynamic_cast<AlphaSystem *>(system); 638319Ssteve.reinhardt@amd.com assert(alphaSystem); 648319Ssteve.reinhardt@amd.com alphaSystem->setIntrFreq(io->frequency()); 658319Ssteve.reinhardt@amd.com} 667047Snate@binkert.org 678319Ssteve.reinhardt@amd.comvoid 688319Ssteve.reinhardt@amd.comTsunami::postConsoleInt() 697047Snate@binkert.org{ 707047Snate@binkert.org io->postPIC(0x10); 718319Ssteve.reinhardt@amd.com} 728319Ssteve.reinhardt@amd.com 738319Ssteve.reinhardt@amd.comvoid 747047Snate@binkert.orgTsunami::clearConsoleInt() 757047Snate@binkert.org{ 767047Snate@binkert.org io->clearPIC(0x10); 771897Sstever@eecs.umich.edu} 781897Sstever@eecs.umich.edu 791897Sstever@eecs.umich.eduvoid 801897Sstever@eecs.umich.eduTsunami::postPciInt(int line) 818319Ssteve.reinhardt@amd.com{ 828319Ssteve.reinhardt@amd.com cchip->postDRIR(line); 838319Ssteve.reinhardt@amd.com} 848319Ssteve.reinhardt@amd.com 858319Ssteve.reinhardt@amd.comvoid 868319Ssteve.reinhardt@amd.comTsunami::clearPciInt(int line) 878319Ssteve.reinhardt@amd.com{ 881897Sstever@eecs.umich.edu cchip->clearDRIR(line); 898319Ssteve.reinhardt@amd.com} 908811Sandreas.hansson@arm.com 918319Ssteve.reinhardt@amd.comAddr 928319Ssteve.reinhardt@amd.comTsunami::pciToDma(Addr pciAddr) const 931897Sstever@eecs.umich.edu{ 947047Snate@binkert.org return pchip->translatePciToDma(pciAddr); 957047Snate@binkert.org} 961897Sstever@eecs.umich.edu 971897Sstever@eecs.umich.edu 984961Ssaidi@eecs.umich.eduAddr 994961Ssaidi@eecs.umich.eduTsunami::calcPciConfigAddr(int bus, int dev, int func) 1004961Ssaidi@eecs.umich.edu{ 1014961Ssaidi@eecs.umich.edu return pchip->calcConfigAddr(bus, dev, func); 1024961Ssaidi@eecs.umich.edu} 1034961Ssaidi@eecs.umich.edu 1044961Ssaidi@eecs.umich.eduAddr 1054961Ssaidi@eecs.umich.eduTsunami::calcPciIOAddr(Addr addr) 1064961Ssaidi@eecs.umich.edu{ 1074961Ssaidi@eecs.umich.edu return pchip->calcIOAddr(addr); 1084961Ssaidi@eecs.umich.edu} 1094961Ssaidi@eecs.umich.edu 1104961Ssaidi@eecs.umich.eduAddr 1114961Ssaidi@eecs.umich.eduTsunami::calcPciMemAddr(Addr addr) 1121897Sstever@eecs.umich.edu{ 1138319Ssteve.reinhardt@amd.com return pchip->calcMemAddr(addr); 1141897Sstever@eecs.umich.edu} 1158319Ssteve.reinhardt@amd.com 1168319Ssteve.reinhardt@amd.comvoid 1178816Sgblack@eecs.umich.eduTsunami::serialize(CheckpointOut &cp) const 1188319Ssteve.reinhardt@amd.com{ 1198319Ssteve.reinhardt@amd.com SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); 1208319Ssteve.reinhardt@amd.com} 1218811Sandreas.hansson@arm.com 1224961Ssaidi@eecs.umich.eduvoid 1238319Ssteve.reinhardt@amd.comTsunami::unserialize(CheckpointIn &cp) 1248811Sandreas.hansson@arm.com{ 1258814Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); 1268319Ssteve.reinhardt@amd.com} 1278811Sandreas.hansson@arm.com 1288811Sandreas.hansson@arm.comTsunami * 1298811Sandreas.hansson@arm.comTsunamiParams::create() 1308811Sandreas.hansson@arm.com{ 1318811Sandreas.hansson@arm.com return new Tsunami(this); 1328811Sandreas.hansson@arm.com} 1338811Sandreas.hansson@arm.com