backdoor.hh revision 843 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* @file
30 * System Console Interface
31 */
32
33#ifndef __ALPHA_CONSOLE_HH__
34#define __ALPHA_CONSOLE_HH__
35
36#include "base/range.hh"
37#include "dev/alpha_access.h"
38#include "dev/io_device.hh"
39#include "sim/host.hh"
40#include "dev/tsunami_io.hh"
41#include "sim/sim_object.hh"
42
43class BaseCPU;
44class SimConsole;
45class System;
46class TlaserClock;
47class SimpleDisk;
48
49/*
50 * Memory mapped interface to the system console. This device
51 * represents a shared data region between the OS Kernel and the
52 * System Console.
53 *
54 * The system console is a small standalone program that is initially
55 * run when the system boots.  It contains the necessary code to
56 * access the boot disk, to read/write from the console, and to pass
57 * boot parameters to the kernel.
58 *
59 * This version of the system console is very different from the one
60 * that would be found in a real system.  Many of the functions use
61 * some sort of backdoor to get their job done.  For example, reading
62 * from the boot device on a real system would require a minimal
63 * device driver to access the disk controller, but since we have a
64 * simulator here, we are able to bypass the disk controller and
65 * access the disk image directly.  There are also some things like
66 * reading the kernel off the disk image into memory that are normally
67 * taken care of by the console that are now taken care of by the
68 * simulator.
69 *
70 * These shortcuts are acceptable since the system console is
71 * primarily used doing boot before the kernel has loaded its device
72 * drivers.
73 */
74class AlphaConsole : public PioDevice
75{
76  protected:
77    union {
78        AlphaAccess *alphaAccess;
79        uint8_t *consoleData;
80    };
81
82    /** the disk must be accessed from the console */
83    SimpleDisk *disk;
84
85    /** the system console (the terminal) is accessable from the console */
86    SimConsole *console;
87
88    Addr addr;
89    static const Addr size = 0x80; // equal to sizeof(alpha_access);
90
91  public:
92    /** Standard Constructor */
93    AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
94                 System *system, BaseCPU *cpu, SimObject *clock,
95                 int num_cpus, MemoryController *mmu, Addr addr,
96                 HierParams *hier, Bus *bus);
97
98    /**
99     * memory mapped reads and writes
100     */
101    virtual Fault read(MemReqPtr &req, uint8_t *data);
102    virtual Fault write(MemReqPtr &req, const uint8_t *data);
103
104    /**
105     * standard serialization routines for checkpointing
106     */
107    virtual void serialize(std::ostream &os);
108    virtual void unserialize(Checkpoint *cp, const std::string &section);
109
110  public:
111    Tick cacheAccess(MemReqPtr &req);
112};
113
114#endif // __ALPHA_CONSOLE_HH__
115