access.h revision 1762
17753SWilliam.Wang@arm.com/* 210839Sandreas.sandberg@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 37753SWilliam.Wang@arm.com * All rights reserved. 47753SWilliam.Wang@arm.com * 57753SWilliam.Wang@arm.com * Redistribution and use in source and binary forms, with or without 67753SWilliam.Wang@arm.com * modification, are permitted provided that the following conditions are 77753SWilliam.Wang@arm.com * met: redistributions of source code must retain the above copyright 87753SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer; 97753SWilliam.Wang@arm.com * redistributions in binary form must reproduce the above copyright 107753SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer in the 117753SWilliam.Wang@arm.com * documentation and/or other materials provided with the distribution; 127753SWilliam.Wang@arm.com * neither the name of the copyright holders nor the names of its 137753SWilliam.Wang@arm.com * contributors may be used to endorse or promote products derived from 147753SWilliam.Wang@arm.com * this software without specific prior written permission. 157753SWilliam.Wang@arm.com * 167753SWilliam.Wang@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177753SWilliam.Wang@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187753SWilliam.Wang@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197753SWilliam.Wang@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207753SWilliam.Wang@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217753SWilliam.Wang@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227753SWilliam.Wang@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237753SWilliam.Wang@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247753SWilliam.Wang@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257753SWilliam.Wang@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267753SWilliam.Wang@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277753SWilliam.Wang@arm.com */ 287753SWilliam.Wang@arm.com 297753SWilliam.Wang@arm.com#ifndef __ALPHA_ACCESS_H__ 307753SWilliam.Wang@arm.com#define __ALPHA_ACCESS_H__ 317753SWilliam.Wang@arm.com 327753SWilliam.Wang@arm.com/** @file 337753SWilliam.Wang@arm.com * System Console Memory Mapped Register Definition 347753SWilliam.Wang@arm.com */ 357753SWilliam.Wang@arm.com 367753SWilliam.Wang@arm.com#define ALPHA_ACCESS_VERSION (1301) 377753SWilliam.Wang@arm.com 387950SAli.Saidi@ARM.com#ifndef CONSOLE 397753SWilliam.Wang@arm.com#include <iosfwd> 407753SWilliam.Wang@arm.com#include <string> 417753SWilliam.Wang@arm.comclass Checkpoint; 427753SWilliam.Wang@arm.com#endif 437753SWilliam.Wang@arm.com 447753SWilliam.Wang@arm.com// This structure hacked up from simos 457753SWilliam.Wang@arm.comstruct AlphaAccess 467753SWilliam.Wang@arm.com{ 477753SWilliam.Wang@arm.com uint32_t last_offset; // 00: must be first field 487753SWilliam.Wang@arm.com uint32_t version; // 04: 497753SWilliam.Wang@arm.com uint32_t numCPUs; // 08: 5010839Sandreas.sandberg@arm.com uint32_t intrClockFrequency; // 0C: Hz 517753SWilliam.Wang@arm.com uint64_t cpuClock; // 10: MHz 5212230Sgiacomo.travaglini@arm.com uint64_t mem_size; // 18: 5310839Sandreas.sandberg@arm.com 5411359Sandreas@sandberg.pp.se // Loaded kernel 557753SWilliam.Wang@arm.com uint64_t kernStart; // 20: 567753SWilliam.Wang@arm.com uint64_t kernEnd; // 28: 577753SWilliam.Wang@arm.com uint64_t entryPoint; // 30: 587753SWilliam.Wang@arm.com 599330Schander.sudanthi@arm.com // console disk stuff 607753SWilliam.Wang@arm.com uint64_t diskUnit; // 38: 617753SWilliam.Wang@arm.com uint64_t diskCount; // 40: 627753SWilliam.Wang@arm.com uint64_t diskPAddr; // 48: 637753SWilliam.Wang@arm.com uint64_t diskBlock; // 50: 647753SWilliam.Wang@arm.com uint64_t diskOperation; // 58: 657753SWilliam.Wang@arm.com 667753SWilliam.Wang@arm.com // console simple output stuff 677753SWilliam.Wang@arm.com uint64_t outputChar; // 60: Placeholder for output 687753SWilliam.Wang@arm.com uint64_t inputChar; // 68: Placeholder for input 697753SWilliam.Wang@arm.com 707753SWilliam.Wang@arm.com // MP boot 717753SWilliam.Wang@arm.com uint64_t bootStrapImpure; // 70: 727753SWilliam.Wang@arm.com uint32_t bootStrapCPU; // 78: 737753SWilliam.Wang@arm.com uint32_t align2; // 7C: Dummy placeholder for alignment 747753SWilliam.Wang@arm.com 757753SWilliam.Wang@arm.com#ifndef CONSOLE 767753SWilliam.Wang@arm.com void serialize(std::ostream &os); 777753SWilliam.Wang@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 787753SWilliam.Wang@arm.com#endif 797753SWilliam.Wang@arm.com}; 807753SWilliam.Wang@arm.com 817753SWilliam.Wang@arm.com#endif // __ALPHA_ACCESS_H__ 827753SWilliam.Wang@arm.com