Tsunami.py revision 3812
1from m5.params import * 2from m5.proxy import * 3from Device import BasicPioDevice, IsaFake, BadAddr 4from Platform import Platform 5from AlphaConsole import AlphaConsole 6from Uart import Uart8250 7from Pci import PciConfigAll 8from BadDevice import BadDevice 9 10class TsunamiCChip(BasicPioDevice): 11 type = 'TsunamiCChip' 12 tsunami = Param.Tsunami(Parent.any, "Tsunami") 13 14class TsunamiIO(BasicPioDevice): 15 type = 'TsunamiIO' 16 time = Param.UInt64(1136073600, 17 "System time to use (0 for actual time, default is 1/1/06)") 18 tsunami = Param.Tsunami(Parent.any, "Tsunami") 19 frequency = Param.Frequency('1024Hz', "frequency of interrupts") 20 21class TsunamiPChip(BasicPioDevice): 22 type = 'TsunamiPChip' 23 tsunami = Param.Tsunami(Parent.any, "Tsunami") 24 25class Tsunami(Platform): 26 type = 'Tsunami' 27 system = Param.System(Parent.any, "system") 28 29 cchip = TsunamiCChip(pio_addr=0x801a0000000) 30 pchip = TsunamiPChip(pio_addr=0x80180000000) 31 pciconfig = PciConfigAll() 32 fake_sm_chip = IsaFake(pio_addr=0x801fc000370) 33 34 fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) 35 fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) 36 fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) 37 fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) 38 39 fake_ppc = IsaFake(pio_addr=0x801fc0003bc) 40 41 fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) 42 43 fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) 44 fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) 45 fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) 46 fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) 47 fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) 48 fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) 49 fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) 50 fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) 51 fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) 52 fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) 53 54 fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) 55 fake_ata1 = IsaFake(pio_addr=0x801fc000170) 56 57 fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') 58 io = TsunamiIO(pio_addr=0x801fc000000) 59 uart = Uart8250(pio_addr=0x801fc0003f8) 60 console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk) 61 62 # Attach I/O devices to specified bus object. Can't do this 63 # earlier, since the bus object itself is typically defined at the 64 # System level. 65 def attachIO(self, bus): 66 self.cchip.pio = bus.port 67 self.pchip.pio = bus.port 68 self.pciconfig.pio = bus.default 69 bus.responder_set = True 70 bus.responder = self.pciconfig 71 self.fake_sm_chip.pio = bus.port 72 self.fake_uart1.pio = bus.port 73 self.fake_uart2.pio = bus.port 74 self.fake_uart3.pio = bus.port 75 self.fake_uart4.pio = bus.port 76 self.fake_ppc.pio = bus.port 77 self.fake_OROM.pio = bus.port 78 self.fake_pnp_addr.pio = bus.port 79 self.fake_pnp_write.pio = bus.port 80 self.fake_pnp_read0.pio = bus.port 81 self.fake_pnp_read1.pio = bus.port 82 self.fake_pnp_read2.pio = bus.port 83 self.fake_pnp_read3.pio = bus.port 84 self.fake_pnp_read4.pio = bus.port 85 self.fake_pnp_read5.pio = bus.port 86 self.fake_pnp_read6.pio = bus.port 87 self.fake_pnp_read7.pio = bus.port 88 self.fake_ata0.pio = bus.port 89 self.fake_ata1.pio = bus.port 90 self.fb.pio = bus.port 91 self.io.pio = bus.port 92 self.uart.pio = bus.port 93 self.console.pio = bus.port 94