Tsunami.py revision 2916 
1from m5.config import *
2from Device import BasicPioDevice
3from Platform import Platform
4from AlphaConsole import AlphaConsole
5from Uart import Uart8250
6from Pci import PciConfigAll
7from BadDevice import BadDevice
8
9class TsunamiCChip(BasicPioDevice):
10    type = 'TsunamiCChip'
11    tsunami = Param.Tsunami(Parent.any, "Tsunami")
12
13class IsaFake(BasicPioDevice):
14    type = 'IsaFake'
15    pio_size = Param.Addr(0x8, "Size of address range")
16
17class TsunamiIO(BasicPioDevice):
18    type = 'TsunamiIO'
19    time = Param.UInt64(1136073600,
20        "System time to use (0 for actual time, default is 1/1/06)")
21    tsunami = Param.Tsunami(Parent.any, "Tsunami")
22    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
23
24class TsunamiPChip(BasicPioDevice):
25    type = 'TsunamiPChip'
26    tsunami = Param.Tsunami(Parent.any, "Tsunami")
27
28class Tsunami(Platform):
29    type = 'Tsunami'
30    system = Param.System(Parent.any, "system")
31
32    cchip = TsunamiCChip(pio_addr=0x801a0000000)
33    pchip = TsunamiPChip(pio_addr=0x80180000000)
34    pciconfig = PciConfigAll()
35    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
36
37    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
38    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
39    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
40    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
41
42    fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
43
44    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
45
46    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
47    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
48    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
49    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
50    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
51    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
52    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
53    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
54    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
55    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
56
57    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
58    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
59
60    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
61    io = TsunamiIO(pio_addr=0x801fc000000)
62    uart = Uart8250(pio_addr=0x801fc0003f8)
63    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
64
65    # Attach I/O devices to specified bus object.  Can't do this
66    # earlier, since the bus object itself is typically defined at the
67    # System level.
68    def attachIO(self, bus):
69        self.cchip.pio = bus.port
70        self.pchip.pio = bus.port
71        self.pciconfig.pio = bus.default
72        self.fake_sm_chip.pio = bus.port
73        self.fake_uart1.pio = bus.port
74        self.fake_uart2.pio = bus.port
75        self.fake_uart3.pio = bus.port
76        self.fake_uart4.pio = bus.port
77        self.fake_ppc.pio = bus.port
78        self.fake_OROM.pio = bus.port
79        self.fake_pnp_addr.pio = bus.port
80        self.fake_pnp_write.pio = bus.port
81        self.fake_pnp_read0.pio = bus.port
82        self.fake_pnp_read1.pio = bus.port
83        self.fake_pnp_read2.pio = bus.port
84        self.fake_pnp_read3.pio = bus.port
85        self.fake_pnp_read4.pio = bus.port
86        self.fake_pnp_read5.pio = bus.port
87        self.fake_pnp_read6.pio = bus.port
88        self.fake_pnp_read7.pio = bus.port
89        self.fake_ata0.pio = bus.port
90        self.fake_ata1.pio = bus.port
91        self.fb.pio = bus.port
92        self.io.pio = bus.port
93        self.uart.pio = bus.port
94        self.console.pio = bus.port
95