Tsunami.py revision 9338
13560SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 23560SN/A# All rights reserved. 33560SN/A# 43560SN/A# Redistribution and use in source and binary forms, with or without 53560SN/A# modification, are permitted provided that the following conditions are 63560SN/A# met: redistributions of source code must retain the above copyright 73560SN/A# notice, this list of conditions and the following disclaimer; 83560SN/A# redistributions in binary form must reproduce the above copyright 93560SN/A# notice, this list of conditions and the following disclaimer in the 103560SN/A# documentation and/or other materials provided with the distribution; 113560SN/A# neither the name of the copyright holders nor the names of its 123560SN/A# contributors may be used to endorse or promote products derived from 133560SN/A# this software without specific prior written permission. 143560SN/A# 153560SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163560SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173560SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183560SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193560SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203560SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213560SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223560SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233560SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243560SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253560SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263560SN/A# 273560SN/A# Authors: Nathan Binkert 283560SN/A 293560SN/Afrom m5.params import * 303560SN/Afrom m5.proxy import * 313560SN/Afrom BadDevice import BadDevice 323560SN/Afrom AlphaBackdoor import AlphaBackdoor 333560SN/Afrom Device import BasicPioDevice, IsaFake, BadAddr 343560SN/Afrom Pci import PciConfigAll 353560SN/Afrom Platform import Platform 365191Ssaidi@eecs.umich.edufrom Uart import Uart8250 373565Sgblack@eecs.umich.edu 383560SN/Aclass TsunamiCChip(BasicPioDevice): 393560SN/A type = 'TsunamiCChip' 403560SN/A cxx_header = "dev/alpha/tsunami_cchip.hh" 413560SN/A tsunami = Param.Tsunami(Parent.any, "Tsunami") 423560SN/A 433560SN/Aclass TsunamiIO(BasicPioDevice): 443560SN/A type = 'TsunamiIO' 453560SN/A cxx_header = "dev/alpha/tsunami_io.hh" 463560SN/A time = Param.Time('01/01/2009', 473560SN/A "System time to use ('Now' for actual time)") 483560SN/A year_is_bcd = Param.Bool(False, 493560SN/A "The RTC should interpret the year as a BCD value") 503560SN/A tsunami = Param.Tsunami(Parent.any, "Tsunami") 513560SN/A frequency = Param.Frequency('1024Hz', "frequency of interrupts") 523560SN/A 533560SN/Aclass TsunamiPChip(BasicPioDevice): 543560SN/A type = 'TsunamiPChip' 553560SN/A cxx_header = "dev/alpha/tsunami_pchip.hh" 563560SN/A tsunami = Param.Tsunami(Parent.any, "Tsunami") 573560SN/A 583560SN/Aclass Tsunami(Platform): 593560SN/A type = 'Tsunami' 603560SN/A cxx_header = "dev/alpha/tsunami.hh" 613560SN/A system = Param.System(Parent.any, "system") 623560SN/A 633560SN/A cchip = TsunamiCChip(pio_addr=0x801a0000000) 643560SN/A pchip = TsunamiPChip(pio_addr=0x80180000000) 653560SN/A pciconfig = PciConfigAll() 663560SN/A fake_sm_chip = IsaFake(pio_addr=0x801fc000370) 673560SN/A 683560SN/A fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) 693560SN/A fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) 703560SN/A fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) 713560SN/A fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) 723560SN/A 733560SN/A fake_ppc = IsaFake(pio_addr=0x801fc0003bb) 743560SN/A 753560SN/A fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) 763560SN/A 773560SN/A fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) 783560SN/A fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) 793560SN/A fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) 803560SN/A fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) 813560SN/A fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) 823560SN/A fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) 833560SN/A fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) 843560SN/A fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) 853560SN/A fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) 863560SN/A fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) 873560SN/A 883560SN/A fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) 893560SN/A fake_ata1 = IsaFake(pio_addr=0x801fc000170) 903560SN/A 913560SN/A fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') 923560SN/A io = TsunamiIO(pio_addr=0x801fc000000) 933560SN/A uart = Uart8250(pio_addr=0x801fc0003f8) 943560SN/A backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) 953560SN/A 963560SN/A # Attach I/O devices to specified bus object. Can't do this 973560SN/A # earlier, since the bus object itself is typically defined at the 983560SN/A # System level. 993560SN/A def attachIO(self, bus): 1003560SN/A self.cchip.pio = bus.master 1013560SN/A self.pchip.pio = bus.master 1023560SN/A self.pciconfig.pio = bus.default 1033560SN/A bus.use_default_range = True 1043560SN/A self.fake_sm_chip.pio = bus.master 1053560SN/A self.fake_uart1.pio = bus.master 1063560SN/A self.fake_uart2.pio = bus.master 1073560SN/A self.fake_uart3.pio = bus.master 1083560SN/A self.fake_uart4.pio = bus.master 1093560SN/A self.fake_ppc.pio = bus.master 1103560SN/A self.fake_OROM.pio = bus.master 1113560SN/A self.fake_pnp_addr.pio = bus.master 1123560SN/A self.fake_pnp_write.pio = bus.master 1133560SN/A self.fake_pnp_read0.pio = bus.master 1143560SN/A self.fake_pnp_read1.pio = bus.master 1153560SN/A self.fake_pnp_read2.pio = bus.master 1163560SN/A self.fake_pnp_read3.pio = bus.master 1173560SN/A self.fake_pnp_read4.pio = bus.master 1183560SN/A self.fake_pnp_read5.pio = bus.master 1193560SN/A self.fake_pnp_read6.pio = bus.master 1203560SN/A self.fake_pnp_read7.pio = bus.master 1213560SN/A self.fake_ata0.pio = bus.master 1223560SN/A self.fake_ata1.pio = bus.master 1233560SN/A self.fb.pio = bus.master 1243560SN/A self.io.pio = bus.master 1253560SN/A self.uart.pio = bus.master 1263560SN/A self.backdoor.pio = bus.master 1273560SN/A