Device.py revision 13930:c5e728ccd2e2
12SN/A# Copyright (c) 2012-2016 ARM Limited 22188SN/A# All rights reserved. 32SN/A# 42SN/A# The license below extends only to copyright in the software and shall 52SN/A# not be construed as granting a license to any other intellectual 62SN/A# property including but not limited to intellectual property relating 72SN/A# to a hardware implementation of the functionality of the software 82SN/A# licensed hereunder. You may use the software subject to the license 92SN/A# terms below provided that you ensure that this notice is replicated 102SN/A# unmodified and in its entirety in all distributions of the software, 112SN/A# modified or unmodified, in source code or in binary form. 122SN/A# 132SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 142SN/A# All rights reserved. 152SN/A# 162SN/A# Redistribution and use in source and binary forms, with or without 172SN/A# modification, are permitted provided that the following conditions are 182SN/A# met: redistributions of source code must retain the above copyright 192SN/A# notice, this list of conditions and the following disclaimer; 202SN/A# redistributions in binary form must reproduce the above copyright 212SN/A# notice, this list of conditions and the following disclaimer in the 222SN/A# documentation and/or other materials provided with the distribution; 232SN/A# neither the name of the copyright holders nor the names of its 242SN/A# contributors may be used to endorse or promote products derived from 252SN/A# this software without specific prior written permission. 262SN/A# 272665SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292665SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322683Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332683Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352190SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363776Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373776Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 381858SN/A# 392680SN/A# Authors: Nathan Binkert 402683Sktlim@umich.edu# Glenn Bergmans 412395SN/A 422395SN/Afrom m5.params import * 432190SN/Afrom m5.proxy import * 442188SN/Afrom m5.util.fdthelper import * 4556SN/A 46217SN/Afrom m5.objects.ClockedObject import ClockedObject 472SN/A 482SN/Aclass PioDevice(ClockedObject): 492SN/A type = 'PioDevice' 501858SN/A cxx_header = "dev/io_device.hh" 512SN/A abstract = True 521070SN/A pio = SlavePort("Programmed I/O port") 532171SN/A system = Param.System(Parent.any, "System this device is part of") 541070SN/A 551917SN/A def generateBasicPioDeviceNode(self, state, name, pio_addr, 561917SN/A size, interrupts = None): 572521SN/A node = FdtNode("%s@%x" % (name, long(pio_addr))) 582521SN/A node.append(FdtPropertyWords("reg", 592521SN/A state.addrCells(pio_addr) + 603548Sgblack@eecs.umich.edu state.sizeCells(size) )) 613548Sgblack@eecs.umich.edu 623548Sgblack@eecs.umich.edu if interrupts: 633548Sgblack@eecs.umich.edu if any([i < 32 for i in interrupts]): 642330SN/A raise(("Interrupt number smaller than 32 "+ 652330SN/A " in PioDevice %s") % name) 662SN/A 672SN/A # subtracting 32 because Linux assumes that SPIs start at 0, while 68360SN/A # gem5 uses the internal GIC numbering (SPIs start at 32) 692462SN/A node.append(FdtPropertyWords("interrupts", sum( 702420SN/A [[0, i - 32, 4] for i in interrupts], []) )) 712SN/A 722SN/A return node 732SN/A 742683Sktlim@umich.educlass BasicPioDevice(PioDevice): 752683Sktlim@umich.edu type = 'BasicPioDevice' 762683Sktlim@umich.edu cxx_header = "dev/io_device.hh" 772683Sktlim@umich.edu abstract = True 782683Sktlim@umich.edu pio_addr = Param.Addr("Device Address") 792683Sktlim@umich.edu pio_latency = Param.Latency('100ns', "Programmed IO latency") 802683Sktlim@umich.edu 812683Sktlim@umich.educlass DmaDevice(PioDevice): 822683Sktlim@umich.edu type = 'DmaDevice' 832683Sktlim@umich.edu cxx_header = "dev/dma_device.hh" 842683Sktlim@umich.edu abstract = True 852683Sktlim@umich.edu dma = MasterPort("DMA port") 862683Sktlim@umich.edu 872683Sktlim@umich.edu sid = Param.Unsigned(0, 882683Sktlim@umich.edu "Stream identifier used by an IOMMU to distinguish amongst " 892SN/A "several devices attached to it") 902683Sktlim@umich.edu ssid = Param.Unsigned(0, 912SN/A "Substream identifier used by an IOMMU to distinguish amongst " 922107SN/A "several devices attached to it") 932107SN/A 942107SN/A 952107SN/Aclass IsaFake(BasicPioDevice): 962159SN/A type = 'IsaFake' 972455SN/A cxx_header = "dev/isa_fake.hh" 982455SN/A pio_size = Param.Addr(0x8, "Size of address range") 992SN/A ret_data8 = Param.UInt8(0xFF, "Default data to return") 1002680SN/A ret_data16 = Param.UInt16(0xFFFF, "Default data to return") 1012SN/A ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") 1022190SN/A ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") 1032SN/A ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 1042SN/A update_data = Param.Bool(False, "Update the data that is returned on writes") 1052190SN/A warn_access = Param.String("", "String to print when device is accessed") 1062683Sktlim@umich.edu fake_mem = Param.Bool(False, 1072SN/A "Is this device acting like a memory and thus may get a cache line sized req") 1082SN/A 1092683Sktlim@umich.educlass BadAddr(IsaFake): 1102188SN/A pio_addr = 0 1112378SN/A ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") 1122400SN/A 1131858SN/A 1143453Sgblack@eecs.umich.edu