Device.py revision 12472:3cbae56f402d
12381SN/A# Copyright (c) 2012-2016 ARM Limited 29542Sandreas.hansson@arm.com# All rights reserved. 38949Sandreas.hansson@arm.com# 48949Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58949Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68949Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78949Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88949Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98949Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108949Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118949Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128949Sandreas.hansson@arm.com# 138949Sandreas.hansson@arm.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 142592SN/A# All rights reserved. 157636Ssteve.reinhardt@amd.com# 162381SN/A# Redistribution and use in source and binary forms, with or without 172381SN/A# modification, are permitted provided that the following conditions are 182381SN/A# met: redistributions of source code must retain the above copyright 192381SN/A# notice, this list of conditions and the following disclaimer; 202381SN/A# redistributions in binary form must reproduce the above copyright 212381SN/A# notice, this list of conditions and the following disclaimer in the 222381SN/A# documentation and/or other materials provided with the distribution; 232381SN/A# neither the name of the copyright holders nor the names of its 242381SN/A# contributors may be used to endorse or promote products derived from 252381SN/A# this software without specific prior written permission. 262381SN/A# 272381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302381SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312381SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322381SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332381SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342381SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352381SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362381SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372381SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382381SN/A# 392381SN/A# Authors: Nathan Binkert 402665Ssaidi@eecs.umich.edu# Glenn Bergmans 412665Ssaidi@eecs.umich.edu 422665Ssaidi@eecs.umich.edufrom m5.params import * 432665Ssaidi@eecs.umich.edufrom m5.proxy import * 449031Sandreas.hansson@arm.comfrom m5.util.fdthelper import * 452381SN/Afrom MemObject import MemObject 462381SN/A 472381SN/Aclass PioDevice(MemObject): 482381SN/A type = 'PioDevice' 492662Sstever@eecs.umich.edu cxx_header = "dev/io_device.hh" 502381SN/A abstract = True 512381SN/A pio = SlavePort("Programmed I/O port") 522381SN/A system = Param.System(Parent.any, "System this device is part of") 532381SN/A 542381SN/A def generateBasicPioDeviceNode(self, state, name, pio_addr, 558229Snate@binkert.org size, interrupts = None): 563348Sbinkertn@umich.edu node = FdtNode("%s@%x" % (name, long(pio_addr))) 573348Sbinkertn@umich.edu node.append(FdtPropertyWords("reg", 583348Sbinkertn@umich.edu state.addrCells(pio_addr) + 595735Snate@binkert.org state.sizeCells(size) )) 604024Sbinkertn@umich.edu 615735Snate@binkert.org if interrupts: 623940Ssaidi@eecs.umich.edu if any([i < 32 for i in interrupts]): 635314Sstever@gmail.com raise(("Interrupt number smaller than 32 "+ 646216Snate@binkert.org " in PioDevice %s") % name) 652392SN/A 664167Sbinkertn@umich.edu # subtracting 32 because Linux assumes that SPIs start at 0, while 672394SN/A # gem5 uses the internal GIC numbering (SPIs start at 32) 688737Skoansin.tan@gmail.com node.append(FdtPropertyWords("interrupts", sum( 693349Sbinkertn@umich.edu [[0, i - 32, 4] for i in interrupts], []) )) 702394SN/A 712812Srdreslin@umich.edu return node 722812Srdreslin@umich.edu 734022Sstever@eecs.umich.educlass BasicPioDevice(PioDevice): 744022Sstever@eecs.umich.edu type = 'BasicPioDevice' 755735Snate@binkert.org cxx_header = "dev/io_device.hh" 765735Snate@binkert.org abstract = True 774022Sstever@eecs.umich.edu pio_addr = Param.Addr("Device Address") 785735Snate@binkert.org pio_latency = Param.Latency('100ns', "Programmed IO latency") 795735Snate@binkert.org 805735Snate@binkert.orgclass DmaDevice(PioDevice): 814022Sstever@eecs.umich.edu type = 'DmaDevice' 824022Sstever@eecs.umich.edu cxx_header = "dev/dma_device.hh" 834022Sstever@eecs.umich.edu abstract = True 844022Sstever@eecs.umich.edu dma = MasterPort("DMA port") 854473Sstever@eecs.umich.edu 865319Sstever@gmail.com 874022Sstever@eecs.umich.educlass IsaFake(BasicPioDevice): 884022Sstever@eecs.umich.edu type = 'IsaFake' 894022Sstever@eecs.umich.edu cxx_header = "dev/isa_fake.hh" 904022Sstever@eecs.umich.edu pio_size = Param.Addr(0x8, "Size of address range") 914022Sstever@eecs.umich.edu ret_data8 = Param.UInt8(0xFF, "Default data to return") 924022Sstever@eecs.umich.edu ret_data16 = Param.UInt16(0xFFFF, "Default data to return") 934022Sstever@eecs.umich.edu ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") 949018Sandreas.hansson@arm.com ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") 959018Sandreas.hansson@arm.com ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 969018Sandreas.hansson@arm.com update_data = Param.Bool(False, "Update the data that is returned on writes") 979018Sandreas.hansson@arm.com warn_access = Param.String("", "String to print when device is accessed") 989018Sandreas.hansson@arm.com fake_mem = Param.Bool(False, 999018Sandreas.hansson@arm.com "Is this device acting like a memory and thus may get a cache line sized req") 1009018Sandreas.hansson@arm.com 1019018Sandreas.hansson@arm.comclass BadAddr(IsaFake): 1024022Sstever@eecs.umich.edu pio_addr = 0 1034022Sstever@eecs.umich.edu ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") 1044022Sstever@eecs.umich.edu 1057465Ssteve.reinhardt@amd.com 1064628Sstever@eecs.umich.edu