trace_cpu.hh revision 2632:1bb2f91485ea
112967Smatteo.andreozzi@arm.com/* 212967Smatteo.andreozzi@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 312967Smatteo.andreozzi@arm.com * All rights reserved. 412967Smatteo.andreozzi@arm.com * 512967Smatteo.andreozzi@arm.com * Redistribution and use in source and binary forms, with or without 612967Smatteo.andreozzi@arm.com * modification, are permitted provided that the following conditions are 712967Smatteo.andreozzi@arm.com * met: redistributions of source code must retain the above copyright 812967Smatteo.andreozzi@arm.com * notice, this list of conditions and the following disclaimer; 912967Smatteo.andreozzi@arm.com * redistributions in binary form must reproduce the above copyright 1012967Smatteo.andreozzi@arm.com * notice, this list of conditions and the following disclaimer in the 1112967Smatteo.andreozzi@arm.com * documentation and/or other materials provided with the distribution; 1212967Smatteo.andreozzi@arm.com * neither the name of the copyright holders nor the names of its 1312967Smatteo.andreozzi@arm.com * contributors may be used to endorse or promote products derived from 1412967Smatteo.andreozzi@arm.com * this software without specific prior written permission. 1512967Smatteo.andreozzi@arm.com * 1612967Smatteo.andreozzi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712967Smatteo.andreozzi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812967Smatteo.andreozzi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912967Smatteo.andreozzi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012967Smatteo.andreozzi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112967Smatteo.andreozzi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212967Smatteo.andreozzi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312967Smatteo.andreozzi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412967Smatteo.andreozzi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512967Smatteo.andreozzi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612967Smatteo.andreozzi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712967Smatteo.andreozzi@arm.com */ 2812967Smatteo.andreozzi@arm.com 2912967Smatteo.andreozzi@arm.com/** 3012967Smatteo.andreozzi@arm.com * @file 3112967Smatteo.andreozzi@arm.com * Declaration of a memory trace CPU object. Uses a memory trace to drive the 3212967Smatteo.andreozzi@arm.com * provided memory hierarchy. 3312967Smatteo.andreozzi@arm.com */ 3412967Smatteo.andreozzi@arm.com 3512967Smatteo.andreozzi@arm.com#ifndef __CPU_TRACE_TRACE_CPU_HH__ 3612967Smatteo.andreozzi@arm.com#define __CPU_TRACE_TRACE_CPU_HH__ 3712967Smatteo.andreozzi@arm.com 3812967Smatteo.andreozzi@arm.com#include <string> 3913665Sandreas.sandberg@arm.com 4012967Smatteo.andreozzi@arm.com#include "mem/mem_req.hh" // for MemReqPtr 4112967Smatteo.andreozzi@arm.com#include "sim/eventq.hh" // for Event 4212967Smatteo.andreozzi@arm.com#include "sim/sim_object.hh" 4312967Smatteo.andreozzi@arm.com 4412967Smatteo.andreozzi@arm.com// Forward declaration. 4512967Smatteo.andreozzi@arm.comclass MemInterface; 4612967Smatteo.andreozzi@arm.comclass MemTraceReader; 4712967Smatteo.andreozzi@arm.com 4812967Smatteo.andreozzi@arm.com/** 4912967Smatteo.andreozzi@arm.com * A cpu object for running memory traces through a memory hierarchy. 5012967Smatteo.andreozzi@arm.com */ 5112967Smatteo.andreozzi@arm.comclass TraceCPU : public SimObject 5212967Smatteo.andreozzi@arm.com{ 5312967Smatteo.andreozzi@arm.com private: 5412967Smatteo.andreozzi@arm.com /** Interface for instruction trace requests, if any. */ 5512967Smatteo.andreozzi@arm.com MemInterface *icacheInterface; 5612967Smatteo.andreozzi@arm.com /** Interface for data trace requests, if any. */ 5712967Smatteo.andreozzi@arm.com MemInterface *dcacheInterface; 5812967Smatteo.andreozzi@arm.com 5912967Smatteo.andreozzi@arm.com /** Data reference trace. */ 6012967Smatteo.andreozzi@arm.com MemTraceReader *dataTrace; 6112967Smatteo.andreozzi@arm.com 6212967Smatteo.andreozzi@arm.com /** Number of outstanding requests. */ 6312967Smatteo.andreozzi@arm.com int outstandingRequests; 64 65 /** Cycle of the next request, 0 if not available. */ 66 Tick nextCycle; 67 68 /** Next request. */ 69 MemReqPtr nextReq; 70 71 /** 72 * Event to call the TraceCPU::tick 73 */ 74 class TickEvent : public Event 75 { 76 private: 77 /** The associated CPU */ 78 TraceCPU *cpu; 79 80 public: 81 /** 82 * Construct this event; 83 */ 84 TickEvent(TraceCPU *c); 85 86 /** 87 * Call the tick function. 88 */ 89 void process(); 90 91 /** 92 * Return a string description of this event. 93 */ 94 const char *description(); 95 }; 96 97 TickEvent tickEvent; 98 99 public: 100 /** 101 * Construct a TraceCPU object. 102 */ 103 TraceCPU(const std::string &name, 104 MemInterface *icache_interface, 105 MemInterface *dcache_interface, 106 MemTraceReader *data_trace); 107 108 inline Tick cycles(int numCycles) { return numCycles; } 109 110 /** 111 * Perform all the accesses for one cycle. 112 */ 113 void tick(); 114 115 /** 116 * Handle a completed memory request. 117 */ 118 void completeRequest(MemReqPtr &req); 119}; 120 121class TraceCompleteEvent : public Event 122{ 123 MemReqPtr req; 124 TraceCPU *tester; 125 126 public: 127 128 TraceCompleteEvent(MemReqPtr &_req, TraceCPU *_tester) 129 : Event(&mainEventQueue), req(_req), tester(_tester) 130 { 131 setFlags(AutoDelete); 132 } 133 134 void process(); 135 136 virtual const char *description(); 137}; 138 139#endif // __CPU_TRACE_TRACE_CPU_HH__ 140 141