thread_state.hh revision 3675
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 57087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org * modification, are permitted provided that the following conditions are 77087Snate@binkert.org * met: redistributions of source code must retain the above copyright 87087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org * documentation and/or other materials provided with the distribution; 127087Snate@binkert.org * neither the name of the copyright holders nor the names of its 134120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147087Snate@binkert.org * this software without specific prior written permission. 157087Snate@binkert.org * 167087Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274120Sgblack@eecs.umich.edu * 284120Sgblack@eecs.umich.edu * Authors: Kevin Lim 294120Sgblack@eecs.umich.edu */ 304120Sgblack@eecs.umich.edu 314120Sgblack@eecs.umich.edu#ifndef __CPU_THREAD_STATE_HH__ 324120Sgblack@eecs.umich.edu#define __CPU_THREAD_STATE_HH__ 334120Sgblack@eecs.umich.edu 344120Sgblack@eecs.umich.edu#include "arch/types.hh" 354120Sgblack@eecs.umich.edu#include "cpu/profile.hh" 364120Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 374120Sgblack@eecs.umich.edu 384120Sgblack@eecs.umich.edu#if !FULL_SYSTEM 394120Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 404120Sgblack@eecs.umich.edu#include "sim/process.hh" 414120Sgblack@eecs.umich.edu#endif 424120Sgblack@eecs.umich.edu 435857Sgblack@eecs.umich.edu#if FULL_SYSTEM 444139Sgblack@eecs.umich.educlass EndQuiesceEvent; 454135Sgblack@eecs.umich.educlass FunctionProfile; 466023Snate@binkert.orgclass ProfileNode; 474120Sgblack@eecs.umich.edunamespace TheISA { 485909Sgblack@eecs.umich.edu namespace Kernel { 495909Sgblack@eecs.umich.edu class Statistics; 504120Sgblack@eecs.umich.edu }; 514120Sgblack@eecs.umich.edu}; 525114Sgblack@eecs.umich.edu#endif 535114Sgblack@eecs.umich.edu 544135Sgblack@eecs.umich.educlass BaseCPU; 554365Sgblack@eecs.umich.educlass Checkpoint; 565114Sgblack@eecs.umich.educlass Port; 575114Sgblack@eecs.umich.educlass TranslatingPort; 585851Sgblack@eecs.umich.edu 595139Sgblack@eecs.umich.edu/** 605114Sgblack@eecs.umich.edu * Struct for holding general thread state that is needed across CPU 615139Sgblack@eecs.umich.edu * models. This includes things such as pointers to the process, 626009Snate@binkert.org * memory, quiesce events, and certain stats. This can be expanded 636009Snate@binkert.org * to hold more thread-specific stats within it. 646009Snate@binkert.org */ 655114Sgblack@eecs.umich.edustruct ThreadState { 665114Sgblack@eecs.umich.edu typedef ThreadContext::Status Status; 675114Sgblack@eecs.umich.edu 684729Sgblack@eecs.umich.edu#if FULL_SYSTEM 694365Sgblack@eecs.umich.edu ThreadState(BaseCPU *cpu, int _cpuId, int _tid); 705114Sgblack@eecs.umich.edu#else 714365Sgblack@eecs.umich.edu ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 724365Sgblack@eecs.umich.edu short _asid); 735114Sgblack@eecs.umich.edu#endif 745114Sgblack@eecs.umich.edu 755114Sgblack@eecs.umich.edu ~ThreadState(); 765114Sgblack@eecs.umich.edu 775114Sgblack@eecs.umich.edu void serialize(std::ostream &os); 785114Sgblack@eecs.umich.edu 795114Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 805114Sgblack@eecs.umich.edu 815114Sgblack@eecs.umich.edu void setCpuId(int id) { cpuId = id; } 825684Sgblack@eecs.umich.edu 835858Sgblack@eecs.umich.edu int readCpuId() { return cpuId; } 845684Sgblack@eecs.umich.edu 855858Sgblack@eecs.umich.edu void setTid(int id) { tid = id; } 865684Sgblack@eecs.umich.edu 875858Sgblack@eecs.umich.edu int readTid() { return tid; } 885858Sgblack@eecs.umich.edu 897678Sgblack@eecs.umich.edu Tick readLastActivate() { return lastActivate; } 907678Sgblack@eecs.umich.edu 915909Sgblack@eecs.umich.edu Tick readLastSuspend() { return lastSuspend; } 925909Sgblack@eecs.umich.edu 935858Sgblack@eecs.umich.edu#if FULL_SYSTEM 945114Sgblack@eecs.umich.edu void init(); 955114Sgblack@eecs.umich.edu 965114Sgblack@eecs.umich.edu void initPhysPort(); 975114Sgblack@eecs.umich.edu 985114Sgblack@eecs.umich.edu void initVirtPort(); 995114Sgblack@eecs.umich.edu 1005114Sgblack@eecs.umich.edu void dumpFuncProfile(); 1015139Sgblack@eecs.umich.edu 1026009Snate@binkert.org EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 1036009Snate@binkert.org 1045114Sgblack@eecs.umich.edu void profileClear(); 1055114Sgblack@eecs.umich.edu 1065114Sgblack@eecs.umich.edu void profileSample(); 1075114Sgblack@eecs.umich.edu 1085114Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 1095114Sgblack@eecs.umich.edu 1105114Sgblack@eecs.umich.edu FunctionalPort *getPhysPort() { return physPort; } 1115114Sgblack@eecs.umich.edu 1125139Sgblack@eecs.umich.edu void setPhysPort(FunctionalPort *port) { physPort = port; } 1136009Snate@binkert.org 1146009Snate@binkert.org VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; } 1155114Sgblack@eecs.umich.edu 1165114Sgblack@eecs.umich.edu void setVirtPort(VirtualPort *port) { virtPort = port; } 1175114Sgblack@eecs.umich.edu#else 1187678Sgblack@eecs.umich.edu Process *getProcessPtr() { return process; } 1197678Sgblack@eecs.umich.edu 1205114Sgblack@eecs.umich.edu TranslatingPort *getMemPort(); 1215114Sgblack@eecs.umich.edu 1225114Sgblack@eecs.umich.edu void setMemPort(TranslatingPort *_port) { port = _port; } 1235114Sgblack@eecs.umich.edu 1245114Sgblack@eecs.umich.edu int getInstAsid() { return asid; } 1255114Sgblack@eecs.umich.edu int getDataAsid() { return asid; } 1265114Sgblack@eecs.umich.edu#endif 1275139Sgblack@eecs.umich.edu 1286009Snate@binkert.org /** Sets the current instruction being committed. */ 1296009Snate@binkert.org void setInst(TheISA::MachInst _inst) { inst = _inst; } 1305114Sgblack@eecs.umich.edu 1315114Sgblack@eecs.umich.edu /** Returns the current instruction being committed. */ 1325114Sgblack@eecs.umich.edu TheISA::MachInst getInst() { return inst; } 1337678Sgblack@eecs.umich.edu 1347678Sgblack@eecs.umich.edu /** Reads the number of instructions functionally executed and 1355114Sgblack@eecs.umich.edu * committed. 1365114Sgblack@eecs.umich.edu */ 1375114Sgblack@eecs.umich.edu Counter readFuncExeInst() { return funcExeInst; } 1385114Sgblack@eecs.umich.edu 1395114Sgblack@eecs.umich.edu /** Sets the total number of instructions functionally executed 1405114Sgblack@eecs.umich.edu * and committed. 1415114Sgblack@eecs.umich.edu */ 1425851Sgblack@eecs.umich.edu void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 1436009Snate@binkert.org 1446009Snate@binkert.org /** Returns the status of this thread. */ 1455114Sgblack@eecs.umich.edu Status status() const { return _status; } 1464135Sgblack@eecs.umich.edu 1474150Sgblack@eecs.umich.edu /** Sets the status of this thread. */ 1484365Sgblack@eecs.umich.edu void setStatus(Status new_status) { _status = new_status; } 1494365Sgblack@eecs.umich.edu 1504365Sgblack@eecs.umich.edu public: 1514729Sgblack@eecs.umich.edu /** Connects port to the functional port of the memory object 1524365Sgblack@eecs.umich.edu * below the CPU. */ 1534365Sgblack@eecs.umich.edu void connectToMemFunc(Port *port); 1544365Sgblack@eecs.umich.edu 1554365Sgblack@eecs.umich.edu /** Number of instructions committed. */ 1567678Sgblack@eecs.umich.edu Counter numInst; 1577678Sgblack@eecs.umich.edu /** Stat for number instructions committed. */ 1584365Sgblack@eecs.umich.edu Stats::Scalar<> numInsts; 1594365Sgblack@eecs.umich.edu /** Stat for number of memory references. */ 1604365Sgblack@eecs.umich.edu Stats::Scalar<> numMemRefs; 1614365Sgblack@eecs.umich.edu 1624365Sgblack@eecs.umich.edu /** Number of simulated loads, used for tracking events based on 1635114Sgblack@eecs.umich.edu * the number of loads committed. 1645114Sgblack@eecs.umich.edu */ 1655114Sgblack@eecs.umich.edu Counter numLoad; 1665114Sgblack@eecs.umich.edu 1675114Sgblack@eecs.umich.edu /** The number of simulated loads committed prior to this run. */ 1685114Sgblack@eecs.umich.edu Counter startNumLoad; 1695114Sgblack@eecs.umich.edu 1705114Sgblack@eecs.umich.edu protected: 1715114Sgblack@eecs.umich.edu ThreadContext::Status _status; 1725114Sgblack@eecs.umich.edu 1735114Sgblack@eecs.umich.edu // Pointer to the base CPU. 1745114Sgblack@eecs.umich.edu BaseCPU *baseCpu; 1755114Sgblack@eecs.umich.edu 1765114Sgblack@eecs.umich.edu // ID of this context w.r.t. the System or Process object to which 1775114Sgblack@eecs.umich.edu // it belongs. For full-system mode, this is the system CPU ID. 1785114Sgblack@eecs.umich.edu int cpuId; 1795114Sgblack@eecs.umich.edu 1805114Sgblack@eecs.umich.edu // Index of hardware thread context on the CPU that this represents. 1815114Sgblack@eecs.umich.edu int tid; 1825114Sgblack@eecs.umich.edu 1835114Sgblack@eecs.umich.edu public: 1845114Sgblack@eecs.umich.edu /** Last time activate was called on this thread. */ 1855114Sgblack@eecs.umich.edu Tick lastActivate; 1865114Sgblack@eecs.umich.edu 1875114Sgblack@eecs.umich.edu /** Last time suspend was called on this thread. */ 1885114Sgblack@eecs.umich.edu Tick lastSuspend; 1895114Sgblack@eecs.umich.edu 1905114Sgblack@eecs.umich.edu#if FULL_SYSTEM 1915114Sgblack@eecs.umich.edu public: 1925114Sgblack@eecs.umich.edu FunctionProfile *profile; 1935114Sgblack@eecs.umich.edu ProfileNode *profileNode; 1945114Sgblack@eecs.umich.edu Addr profilePC; 1955114Sgblack@eecs.umich.edu EndQuiesceEvent *quiesceEvent; 1965114Sgblack@eecs.umich.edu 1975114Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *kernelStats; 1985851Sgblack@eecs.umich.edu protected: 1995114Sgblack@eecs.umich.edu /** A functional port outgoing only for functional accesses to physical 2005114Sgblack@eecs.umich.edu * addresses.*/ 2015114Sgblack@eecs.umich.edu FunctionalPort *physPort; 2025114Sgblack@eecs.umich.edu 2035114Sgblack@eecs.umich.edu /** A functional port, outgoing only, for functional accesse to virtual 2045114Sgblack@eecs.umich.edu * addresses. That doen't require execution context information */ 2055114Sgblack@eecs.umich.edu VirtualPort *virtPort; 2065851Sgblack@eecs.umich.edu#else 2075114Sgblack@eecs.umich.edu TranslatingPort *port; 2085114Sgblack@eecs.umich.edu 2095114Sgblack@eecs.umich.edu Process *process; 2105114Sgblack@eecs.umich.edu 2115114Sgblack@eecs.umich.edu // Address space ID. Note that this is used for TIMING cache 2125114Sgblack@eecs.umich.edu // simulation only; all functional memory accesses should use 2135655Sgblack@eecs.umich.edu // one of the FunctionalMemory pointers above. 2145851Sgblack@eecs.umich.edu short asid; 2155114Sgblack@eecs.umich.edu 2165114Sgblack@eecs.umich.edu#endif 2175114Sgblack@eecs.umich.edu 2185114Sgblack@eecs.umich.edu /** Current instruction the thread is committing. Only set and 2195114Sgblack@eecs.umich.edu * used for DTB faults currently. 2205114Sgblack@eecs.umich.edu */ 2215114Sgblack@eecs.umich.edu TheISA::MachInst inst; 2225851Sgblack@eecs.umich.edu 2235114Sgblack@eecs.umich.edu /** The current microcode pc for the currently executing macro 2245114Sgblack@eecs.umich.edu * operation. 2255114Sgblack@eecs.umich.edu */ 2265114Sgblack@eecs.umich.edu MicroPC microPC; 2275114Sgblack@eecs.umich.edu 2285114Sgblack@eecs.umich.edu /** The next microcode pc for the currently executing macro 2295114Sgblack@eecs.umich.edu * operation. 2305851Sgblack@eecs.umich.edu */ 2315114Sgblack@eecs.umich.edu MicroPC nextMicroPC; 2325114Sgblack@eecs.umich.edu 2335114Sgblack@eecs.umich.edu public: 2345114Sgblack@eecs.umich.edu /** 2355114Sgblack@eecs.umich.edu * Temporary storage to pass the source address from copy_load to 2365114Sgblack@eecs.umich.edu * copy_store. 2375114Sgblack@eecs.umich.edu * @todo Remove this temporary when we have a better way to do it. 2385851Sgblack@eecs.umich.edu */ 2395114Sgblack@eecs.umich.edu Addr copySrcAddr; 2405114Sgblack@eecs.umich.edu /** 2415114Sgblack@eecs.umich.edu * Temp storage for the physical source address of a copy. 2425114Sgblack@eecs.umich.edu * @todo Remove this temporary when we have a better way to do it. 2435114Sgblack@eecs.umich.edu */ 2445114Sgblack@eecs.umich.edu Addr copySrcPhysAddr; 2455114Sgblack@eecs.umich.edu 2465851Sgblack@eecs.umich.edu /* 2475114Sgblack@eecs.umich.edu * number of executed instructions, for matching with syscall trace 2487681Sgblack@eecs.umich.edu * points in EIO files. 2497681Sgblack@eecs.umich.edu */ 2507681Sgblack@eecs.umich.edu Counter funcExeInst; 2517681Sgblack@eecs.umich.edu 2527681Sgblack@eecs.umich.edu // 2535114Sgblack@eecs.umich.edu // Count failed store conditionals so we can warn of apparent 2545114Sgblack@eecs.umich.edu // application deadlock situations. 2555114Sgblack@eecs.umich.edu unsigned storeCondFailures; 2565114Sgblack@eecs.umich.edu}; 2575114Sgblack@eecs.umich.edu 2585114Sgblack@eecs.umich.edu#endif // __CPU_THREAD_STATE_HH__ 2595851Sgblack@eecs.umich.edu