thread_state.hh revision 8902
16145SN/A/* 26386SN/A * Copyright (c) 2006 The Regents of The University of Michigan 37553SN/A * All rights reserved. 46386SN/A * 56386SN/A * Redistribution and use in source and binary forms, with or without 66386SN/A * modification, are permitted provided that the following conditions are 76386SN/A * met: redistributions of source code must retain the above copyright 86386SN/A * notice, this list of conditions and the following disclaimer; 96386SN/A * redistributions in binary form must reproduce the above copyright 106386SN/A * notice, this list of conditions and the following disclaimer in the 116386SN/A * documentation and/or other materials provided with the distribution; 126386SN/A * neither the name of the copyright holders nor the names of its 136386SN/A * contributors may be used to endorse or promote products derived from 146386SN/A * this software without specific prior written permission. 156386SN/A * 166386SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176386SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186386SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196386SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206386SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216386SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226386SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236386SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246386SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256386SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266386SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276386SN/A * 286386SN/A * Authors: Kevin Lim 296145SN/A */ 307632SBrad.Beckmann@amd.com 318832SAli.Saidi@ARM.com#ifndef __CPU_THREAD_STATE_HH__ 326145SN/A#define __CPU_THREAD_STATE_HH__ 337553SN/A 348832SAli.Saidi@ARM.com#include "arch/types.hh" 358832SAli.Saidi@ARM.com#include "config/the_isa.hh" 366145SN/A#include "cpu/base.hh" 377553SN/A#include "cpu/profile.hh" 387553SN/A#include "cpu/thread_context.hh" 396145SN/A#include "mem/mem_object.hh" 406145SN/A#include "sim/process.hh" 417553SN/A 427553SN/Aclass EndQuiesceEvent; 436145SN/Aclass FunctionProfile; 447553SN/Aclass ProfileNode; 457553SN/Anamespace TheISA { 466145SN/A namespace Kernel { 47 class Statistics; 48 } 49} 50 51class Checkpoint; 52 53/** 54 * Struct for holding general thread state that is needed across CPU 55 * models. This includes things such as pointers to the process, 56 * memory, quiesce events, and certain stats. This can be expanded 57 * to hold more thread-specific stats within it. 58 */ 59struct ThreadState { 60 typedef ThreadContext::Status Status; 61 62 ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process); 63 64 virtual ~ThreadState(); 65 66 void serialize(std::ostream &os); 67 68 void unserialize(Checkpoint *cp, const std::string §ion); 69 70 int cpuId() { return baseCpu->cpuId(); } 71 72 int contextId() { return _contextId; } 73 74 void setContextId(int id) { _contextId = id; } 75 76 void setThreadId(ThreadID id) { _threadId = id; } 77 78 ThreadID threadId() { return _threadId; } 79 80 Tick readLastActivate() { return lastActivate; } 81 82 Tick readLastSuspend() { return lastSuspend; } 83 84 /** 85 * Initialise the physical and virtual port proxies and tie them to 86 * the data port of the CPU. 87 * 88 * tc ThreadContext for the virtual-to-physical translation 89 */ 90 void initMemProxies(ThreadContext *tc); 91 92 void dumpFuncProfile(); 93 94 EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 95 96 void profileClear(); 97 98 void profileSample(); 99 100 TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } 101 102 PortProxy &getPhysProxy() { return *physProxy; } 103 104 FSTranslatingPortProxy &getVirtProxy() { return *virtProxy; } 105 106 Process *getProcessPtr() { return process; } 107 108 SETranslatingPortProxy &getMemProxy(); 109 110 /** Reads the number of instructions functionally executed and 111 * committed. 112 */ 113 Counter readFuncExeInst() { return funcExeInst; } 114 115 /** Sets the total number of instructions functionally executed 116 * and committed. 117 */ 118 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 119 120 /** Returns the status of this thread. */ 121 Status status() const { return _status; } 122 123 /** Sets the status of this thread. */ 124 void setStatus(Status new_status) { _status = new_status; } 125 126 public: 127 128 /** Number of instructions committed. */ 129 Counter numInst; 130 /** Stat for number instructions committed. */ 131 Stats::Scalar numInsts; 132 /** Number of ops (including micro ops) committed. */ 133 Counter numOp; 134 /** Stat for number ops (including micro ops) committed. */ 135 Stats::Scalar numOps; 136 /** Stat for number of memory references. */ 137 Stats::Scalar numMemRefs; 138 139 /** Number of simulated loads, used for tracking events based on 140 * the number of loads committed. 141 */ 142 Counter numLoad; 143 144 /** The number of simulated loads committed prior to this run. */ 145 Counter startNumLoad; 146 147 protected: 148 ThreadContext::Status _status; 149 150 // Pointer to the base CPU. 151 BaseCPU *baseCpu; 152 153 // system wide HW context id 154 int _contextId; 155 156 // Index of hardware thread context on the CPU that this represents. 157 ThreadID _threadId; 158 159 public: 160 /** Last time activate was called on this thread. */ 161 Tick lastActivate; 162 163 /** Last time suspend was called on this thread. */ 164 Tick lastSuspend; 165 166 public: 167 FunctionProfile *profile; 168 ProfileNode *profileNode; 169 Addr profilePC; 170 EndQuiesceEvent *quiesceEvent; 171 172 TheISA::Kernel::Statistics *kernelStats; 173 174 protected: 175 Process *process; 176 177 /** A port proxy outgoing only for functional accesses to physical 178 * addresses.*/ 179 PortProxy *physProxy; 180 181 /** A translating port proxy, outgoing only, for functional 182 * accesse to virtual addresses. */ 183 FSTranslatingPortProxy *virtProxy; 184 SETranslatingPortProxy *proxy; 185 186 public: 187 /* 188 * number of executed instructions, for matching with syscall trace 189 * points in EIO files. 190 */ 191 Counter funcExeInst; 192 193 // 194 // Count failed store conditionals so we can warn of apparent 195 // application deadlock situations. 196 unsigned storeCondFailures; 197}; 198 199#endif // __CPU_THREAD_STATE_HH__ 200