thread_state.hh revision 3402
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Kevin Lim 2910259SAndrew.Bardsley@arm.com */ 3010259SAndrew.Bardsley@arm.com 3110259SAndrew.Bardsley@arm.com#ifndef __CPU_THREAD_STATE_HH__ 3210259SAndrew.Bardsley@arm.com#define __CPU_THREAD_STATE_HH__ 3310259SAndrew.Bardsley@arm.com 3410259SAndrew.Bardsley@arm.com#include "arch/types.hh" 3510259SAndrew.Bardsley@arm.com#include "cpu/profile.hh" 3610259SAndrew.Bardsley@arm.com#include "cpu/thread_context.hh" 3710259SAndrew.Bardsley@arm.com 3810259SAndrew.Bardsley@arm.com#if !FULL_SYSTEM 3910259SAndrew.Bardsley@arm.com#include "mem/mem_object.hh" 4010259SAndrew.Bardsley@arm.com#include "sim/process.hh" 4110259SAndrew.Bardsley@arm.com#endif 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 4410259SAndrew.Bardsley@arm.comclass EndQuiesceEvent; 4510259SAndrew.Bardsley@arm.comclass FunctionProfile; 4610259SAndrew.Bardsley@arm.comclass ProfileNode; 4710259SAndrew.Bardsley@arm.comnamespace Kernel { 4810259SAndrew.Bardsley@arm.com class Statistics; 4910259SAndrew.Bardsley@arm.com}; 5010259SAndrew.Bardsley@arm.com#endif 5110259SAndrew.Bardsley@arm.com 5210259SAndrew.Bardsley@arm.comclass BaseCPU; 5310259SAndrew.Bardsley@arm.comclass Checkpoint; 5410259SAndrew.Bardsley@arm.comclass TranslatingPort; 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.com/** 5710259SAndrew.Bardsley@arm.com * Struct for holding general thread state that is needed across CPU 5810259SAndrew.Bardsley@arm.com * models. This includes things such as pointers to the process, 5910259SAndrew.Bardsley@arm.com * memory, quiesce events, and certain stats. This can be expanded 6010259SAndrew.Bardsley@arm.com * to hold more thread-specific stats within it. 6110259SAndrew.Bardsley@arm.com */ 6210259SAndrew.Bardsley@arm.comstruct ThreadState { 6310259SAndrew.Bardsley@arm.com typedef ThreadContext::Status Status; 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 6610259SAndrew.Bardsley@arm.com ThreadState(BaseCPU *cpu, int _cpuId, int _tid); 6710259SAndrew.Bardsley@arm.com#else 6810259SAndrew.Bardsley@arm.com ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 6910259SAndrew.Bardsley@arm.com short _asid); 7010259SAndrew.Bardsley@arm.com#endif 7110259SAndrew.Bardsley@arm.com 7210259SAndrew.Bardsley@arm.com void serialize(std::ostream &os); 7310259SAndrew.Bardsley@arm.com 7410259SAndrew.Bardsley@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.com void setCpuId(int id) { cpuId = id; } 7710259SAndrew.Bardsley@arm.com 7810259SAndrew.Bardsley@arm.com int readCpuId() { return cpuId; } 7910259SAndrew.Bardsley@arm.com 8010259SAndrew.Bardsley@arm.com void setTid(int id) { tid = id; } 8110259SAndrew.Bardsley@arm.com 8210259SAndrew.Bardsley@arm.com int readTid() { return tid; } 8310259SAndrew.Bardsley@arm.com 8410259SAndrew.Bardsley@arm.com Tick readLastActivate() { return lastActivate; } 8510259SAndrew.Bardsley@arm.com 8610259SAndrew.Bardsley@arm.com Tick readLastSuspend() { return lastSuspend; } 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 8910259SAndrew.Bardsley@arm.com void dumpFuncProfile(); 9010259SAndrew.Bardsley@arm.com 9110259SAndrew.Bardsley@arm.com EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } 9210259SAndrew.Bardsley@arm.com 9310259SAndrew.Bardsley@arm.com void profileClear(); 9410259SAndrew.Bardsley@arm.com 9510259SAndrew.Bardsley@arm.com void profileSample(); 9610259SAndrew.Bardsley@arm.com 9710259SAndrew.Bardsley@arm.com Kernel::Statistics *getKernelStats() { return kernelStats; } 9810259SAndrew.Bardsley@arm.com 9910259SAndrew.Bardsley@arm.com FunctionalPort *getPhysPort() { return physPort; } 10010259SAndrew.Bardsley@arm.com 10110259SAndrew.Bardsley@arm.com void setPhysPort(FunctionalPort *port) { physPort = port; } 10210259SAndrew.Bardsley@arm.com 10310259SAndrew.Bardsley@arm.com VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; } 10410259SAndrew.Bardsley@arm.com 10510259SAndrew.Bardsley@arm.com void setVirtPort(VirtualPort *port) { virtPort = port; } 10610259SAndrew.Bardsley@arm.com#else 10710259SAndrew.Bardsley@arm.com Process *getProcessPtr() { return process; } 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com TranslatingPort *getMemPort(); 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.com void setMemPort(TranslatingPort *_port) { port = _port; } 11210259SAndrew.Bardsley@arm.com 11310259SAndrew.Bardsley@arm.com int getInstAsid() { return asid; } 11410259SAndrew.Bardsley@arm.com int getDataAsid() { return asid; } 11510259SAndrew.Bardsley@arm.com#endif 11610259SAndrew.Bardsley@arm.com 11710259SAndrew.Bardsley@arm.com /** Sets the current instruction being committed. */ 11810259SAndrew.Bardsley@arm.com void setInst(TheISA::MachInst _inst) { inst = _inst; } 11910259SAndrew.Bardsley@arm.com 12010259SAndrew.Bardsley@arm.com /** Returns the current instruction being committed. */ 12110259SAndrew.Bardsley@arm.com TheISA::MachInst getInst() { return inst; } 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.com /** Reads the number of instructions functionally executed and 12410259SAndrew.Bardsley@arm.com * committed. 12510259SAndrew.Bardsley@arm.com */ 12610259SAndrew.Bardsley@arm.com Counter readFuncExeInst() { return funcExeInst; } 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.com /** Sets the total number of instructions functionally executed 12910259SAndrew.Bardsley@arm.com * and committed. 13010259SAndrew.Bardsley@arm.com */ 13110259SAndrew.Bardsley@arm.com void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.com /** Returns the status of this thread. */ 13410259SAndrew.Bardsley@arm.com Status status() const { return _status; } 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.com /** Sets the status of this thread. */ 13710259SAndrew.Bardsley@arm.com void setStatus(Status new_status) { _status = new_status; } 13810259SAndrew.Bardsley@arm.com 13910259SAndrew.Bardsley@arm.com /** Number of instructions committed. */ 14010259SAndrew.Bardsley@arm.com Counter numInst; 14110259SAndrew.Bardsley@arm.com /** Stat for number instructions committed. */ 14210259SAndrew.Bardsley@arm.com Stats::Scalar<> numInsts; 14310259SAndrew.Bardsley@arm.com /** Stat for number of memory references. */ 14410259SAndrew.Bardsley@arm.com Stats::Scalar<> numMemRefs; 14510259SAndrew.Bardsley@arm.com 14610259SAndrew.Bardsley@arm.com /** Number of simulated loads, used for tracking events based on 14710259SAndrew.Bardsley@arm.com * the number of loads committed. 14810259SAndrew.Bardsley@arm.com */ 14910259SAndrew.Bardsley@arm.com Counter numLoad; 15010259SAndrew.Bardsley@arm.com 15110259SAndrew.Bardsley@arm.com /** The number of simulated loads committed prior to this run. */ 15210259SAndrew.Bardsley@arm.com Counter startNumLoad; 15310259SAndrew.Bardsley@arm.com 15410259SAndrew.Bardsley@arm.com protected: 15510259SAndrew.Bardsley@arm.com ThreadContext::Status _status; 15610259SAndrew.Bardsley@arm.com 15710259SAndrew.Bardsley@arm.com // Pointer to the base CPU. 15810259SAndrew.Bardsley@arm.com BaseCPU *baseCpu; 15910259SAndrew.Bardsley@arm.com 16010259SAndrew.Bardsley@arm.com // ID of this context w.r.t. the System or Process object to which 16110259SAndrew.Bardsley@arm.com // it belongs. For full-system mode, this is the system CPU ID. 16210259SAndrew.Bardsley@arm.com int cpuId; 16310259SAndrew.Bardsley@arm.com 16410259SAndrew.Bardsley@arm.com // Index of hardware thread context on the CPU that this represents. 16510259SAndrew.Bardsley@arm.com int tid; 16610259SAndrew.Bardsley@arm.com 16710259SAndrew.Bardsley@arm.com public: 16810259SAndrew.Bardsley@arm.com /** Last time activate was called on this thread. */ 16910259SAndrew.Bardsley@arm.com Tick lastActivate; 17010259SAndrew.Bardsley@arm.com 17110259SAndrew.Bardsley@arm.com /** Last time suspend was called on this thread. */ 17210259SAndrew.Bardsley@arm.com Tick lastSuspend; 17310259SAndrew.Bardsley@arm.com 17410259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 17510259SAndrew.Bardsley@arm.com public: 17610259SAndrew.Bardsley@arm.com FunctionProfile *profile; 17710259SAndrew.Bardsley@arm.com ProfileNode *profileNode; 17810259SAndrew.Bardsley@arm.com Addr profilePC; 17910259SAndrew.Bardsley@arm.com EndQuiesceEvent *quiesceEvent; 18010259SAndrew.Bardsley@arm.com 18110259SAndrew.Bardsley@arm.com Kernel::Statistics *kernelStats; 18210259SAndrew.Bardsley@arm.com protected: 18310259SAndrew.Bardsley@arm.com /** A functional port outgoing only for functional accesses to physical 18410259SAndrew.Bardsley@arm.com * addresses.*/ 18510259SAndrew.Bardsley@arm.com FunctionalPort *physPort; 18610259SAndrew.Bardsley@arm.com 18710259SAndrew.Bardsley@arm.com /** A functional port, outgoing only, for functional accesse to virtual 18810259SAndrew.Bardsley@arm.com * addresses. That doen't require execution context information */ 18910259SAndrew.Bardsley@arm.com VirtualPort *virtPort; 19010259SAndrew.Bardsley@arm.com#else 19110259SAndrew.Bardsley@arm.com TranslatingPort *port; 19210259SAndrew.Bardsley@arm.com 19310407Smitch.hayenga@arm.com Process *process; 19410407Smitch.hayenga@arm.com 19510407Smitch.hayenga@arm.com // Address space ID. Note that this is used for TIMING cache 19610259SAndrew.Bardsley@arm.com // simulation only; all functional memory accesses should use 19710259SAndrew.Bardsley@arm.com // one of the FunctionalMemory pointers above. 19810259SAndrew.Bardsley@arm.com short asid; 19910259SAndrew.Bardsley@arm.com 20010259SAndrew.Bardsley@arm.com#endif 20110259SAndrew.Bardsley@arm.com 20210259SAndrew.Bardsley@arm.com /** Current instruction the thread is committing. Only set and 20310259SAndrew.Bardsley@arm.com * used for DTB faults currently. 20410259SAndrew.Bardsley@arm.com */ 20510259SAndrew.Bardsley@arm.com TheISA::MachInst inst; 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com /** The current microcode pc for the currently executing macro 20810259SAndrew.Bardsley@arm.com * operation. 20910259SAndrew.Bardsley@arm.com */ 21010259SAndrew.Bardsley@arm.com MicroPC microPC; 21110259SAndrew.Bardsley@arm.com 21210259SAndrew.Bardsley@arm.com /** The next microcode pc for the currently executing macro 21310259SAndrew.Bardsley@arm.com * operation. 21410259SAndrew.Bardsley@arm.com */ 21510259SAndrew.Bardsley@arm.com MicroPC nextMicroPC; 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.com public: 21810259SAndrew.Bardsley@arm.com /** 21910259SAndrew.Bardsley@arm.com * Temporary storage to pass the source address from copy_load to 22010259SAndrew.Bardsley@arm.com * copy_store. 22110259SAndrew.Bardsley@arm.com * @todo Remove this temporary when we have a better way to do it. 22210259SAndrew.Bardsley@arm.com */ 22310259SAndrew.Bardsley@arm.com Addr copySrcAddr; 22410259SAndrew.Bardsley@arm.com /** 22510259SAndrew.Bardsley@arm.com * Temp storage for the physical source address of a copy. 22610259SAndrew.Bardsley@arm.com * @todo Remove this temporary when we have a better way to do it. 22710259SAndrew.Bardsley@arm.com */ 22810259SAndrew.Bardsley@arm.com Addr copySrcPhysAddr; 22910259SAndrew.Bardsley@arm.com 23010259SAndrew.Bardsley@arm.com /* 23110259SAndrew.Bardsley@arm.com * number of executed instructions, for matching with syscall trace 23210259SAndrew.Bardsley@arm.com * points in EIO files. 23310259SAndrew.Bardsley@arm.com */ 23410259SAndrew.Bardsley@arm.com Counter funcExeInst; 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com // 23710259SAndrew.Bardsley@arm.com // Count failed store conditionals so we can warn of apparent 23810259SAndrew.Bardsley@arm.com // application deadlock situations. 23910259SAndrew.Bardsley@arm.com unsigned storeCondFailures; 24010259SAndrew.Bardsley@arm.com}; 24110259SAndrew.Bardsley@arm.com 24210259SAndrew.Bardsley@arm.com#endif // __CPU_THREAD_STATE_HH__ 24310259SAndrew.Bardsley@arm.com