thread_state.cc revision 6331:d947798df4a1 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "base/output.hh"
32#include "cpu/base.hh"
33#include "cpu/profile.hh"
34#include "cpu/thread_state.hh"
35#include "mem/port.hh"
36#include "mem/translating_port.hh"
37#include "sim/serialize.hh"
38
39#if FULL_SYSTEM
40#include "arch/kernel_stats.hh"
41#include "cpu/quiesce_event.hh"
42#include "mem/vport.hh"
43#endif
44
45#if FULL_SYSTEM
46ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid)
47#else
48ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
49#endif
50    : numInst(0), numLoad(0), _status(ThreadContext::Halted),
51      baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
52#if FULL_SYSTEM
53      profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
54      kernelStats(NULL), physPort(NULL), virtPort(NULL),
55#else
56      port(NULL), process(_process),
57#endif
58      funcExeInst(0), storeCondFailures(0)
59{
60}
61
62ThreadState::~ThreadState()
63{
64#if !FULL_SYSTEM
65    if (port) {
66        delete port->getPeer();
67        delete port;
68    }
69#endif
70}
71
72void
73ThreadState::serialize(std::ostream &os)
74{
75    SERIALIZE_ENUM(_status);
76    // thread_num and cpu_id are deterministic from the config
77    SERIALIZE_SCALAR(funcExeInst);
78    SERIALIZE_SCALAR(inst);
79
80#if FULL_SYSTEM
81    Tick quiesceEndTick = 0;
82    if (quiesceEvent->scheduled())
83        quiesceEndTick = quiesceEvent->when();
84    SERIALIZE_SCALAR(quiesceEndTick);
85    if (kernelStats)
86        kernelStats->serialize(os);
87#endif
88}
89
90void
91ThreadState::unserialize(Checkpoint *cp, const std::string &section)
92{
93
94    UNSERIALIZE_ENUM(_status);
95    // thread_num and cpu_id are deterministic from the config
96    UNSERIALIZE_SCALAR(funcExeInst);
97    UNSERIALIZE_SCALAR(inst);
98
99#if FULL_SYSTEM
100    Tick quiesceEndTick;
101    UNSERIALIZE_SCALAR(quiesceEndTick);
102    if (quiesceEndTick)
103        baseCpu->schedule(quiesceEvent, quiesceEndTick);
104    if (kernelStats)
105        kernelStats->unserialize(cp, section);
106#endif
107}
108
109#if FULL_SYSTEM
110void
111ThreadState::connectMemPorts(ThreadContext *tc)
112{
113    connectPhysPort();
114    connectVirtPort(tc);
115}
116
117void
118ThreadState::connectPhysPort()
119{
120    // @todo: For now this disregards any older port that may have
121    // already existed.  Fix this memory leak once the bus port IDs
122    // for functional ports is resolved.
123    if (physPort)
124        physPort->removeConn();
125    else
126        physPort = new FunctionalPort(csprintf("%s-%d-funcport",
127                                           baseCpu->name(), _threadId));
128    connectToMemFunc(physPort);
129}
130
131void
132ThreadState::connectVirtPort(ThreadContext *tc)
133{
134    // @todo: For now this disregards any older port that may have
135    // already existed.  Fix this memory leak once the bus port IDs
136    // for functional ports is resolved.
137    if (virtPort)
138        virtPort->removeConn();
139    else
140        virtPort = new VirtualPort(csprintf("%s-%d-vport",
141                                        baseCpu->name(), _threadId), tc);
142    connectToMemFunc(virtPort);
143}
144
145void
146ThreadState::profileClear()
147{
148    if (profile)
149        profile->clear();
150}
151
152void
153ThreadState::profileSample()
154{
155    if (profile)
156        profile->sample(profileNode, profilePC);
157}
158
159#else
160TranslatingPort *
161ThreadState::getMemPort()
162{
163    if (port != NULL)
164        return port;
165
166    /* Use this port to for syscall emulation writes to memory. */
167    port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), _threadId),
168                               process, TranslatingPort::NextPage);
169
170    connectToMemFunc(port);
171
172    return port;
173}
174#endif
175
176void
177ThreadState::connectToMemFunc(Port *port)
178{
179    Port *dcache_port, *func_mem_port;
180
181    dcache_port = baseCpu->getPort("dcache_port");
182    assert(dcache_port != NULL);
183
184    MemObject *mem_object = dcache_port->getPeer()->getOwner();
185    assert(mem_object != NULL);
186
187    func_mem_port = mem_object->getPort("functional");
188    assert(func_mem_port != NULL);
189
190    func_mem_port->setPeer(port);
191    port->setPeer(func_mem_port);
192}
193