thread_state.cc revision 8852
112966SMatteo.Andreozzi@arm.com/* 212966SMatteo.Andreozzi@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 312966SMatteo.Andreozzi@arm.com * All rights reserved. 412966SMatteo.Andreozzi@arm.com * 512966SMatteo.Andreozzi@arm.com * Redistribution and use in source and binary forms, with or without 612966SMatteo.Andreozzi@arm.com * modification, are permitted provided that the following conditions are 712966SMatteo.Andreozzi@arm.com * met: redistributions of source code must retain the above copyright 812966SMatteo.Andreozzi@arm.com * notice, this list of conditions and the following disclaimer; 912966SMatteo.Andreozzi@arm.com * redistributions in binary form must reproduce the above copyright 1012966SMatteo.Andreozzi@arm.com * notice, this list of conditions and the following disclaimer in the 1112966SMatteo.Andreozzi@arm.com * documentation and/or other materials provided with the distribution; 1212966SMatteo.Andreozzi@arm.com * neither the name of the copyright holders nor the names of its 1312966SMatteo.Andreozzi@arm.com * contributors may be used to endorse or promote products derived from 1412966SMatteo.Andreozzi@arm.com * this software without specific prior written permission. 1512966SMatteo.Andreozzi@arm.com * 1612966SMatteo.Andreozzi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712966SMatteo.Andreozzi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812966SMatteo.Andreozzi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912966SMatteo.Andreozzi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012966SMatteo.Andreozzi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112966SMatteo.Andreozzi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212966SMatteo.Andreozzi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312966SMatteo.Andreozzi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412966SMatteo.Andreozzi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512966SMatteo.Andreozzi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612966SMatteo.Andreozzi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712966SMatteo.Andreozzi@arm.com * 2812966SMatteo.Andreozzi@arm.com * Authors: Kevin Lim 2912966SMatteo.Andreozzi@arm.com */ 3012966SMatteo.Andreozzi@arm.com 3112966SMatteo.Andreozzi@arm.com#include "arch/kernel_stats.hh" 3212966SMatteo.Andreozzi@arm.com#include "base/output.hh" 3312966SMatteo.Andreozzi@arm.com#include "cpu/base.hh" 3412966SMatteo.Andreozzi@arm.com#include "cpu/profile.hh" 3512966SMatteo.Andreozzi@arm.com#include "cpu/quiesce_event.hh" 3612966SMatteo.Andreozzi@arm.com#include "cpu/thread_state.hh" 3712966SMatteo.Andreozzi@arm.com#include "mem/fs_translating_port_proxy.hh" 3812966SMatteo.Andreozzi@arm.com#include "mem/port.hh" 3912966SMatteo.Andreozzi@arm.com#include "mem/port_proxy.hh" 4012966SMatteo.Andreozzi@arm.com#include "mem/se_translating_port_proxy.hh" 4112966SMatteo.Andreozzi@arm.com#include "sim/full_system.hh" 4212966SMatteo.Andreozzi@arm.com#include "sim/serialize.hh" 4312966SMatteo.Andreozzi@arm.com#include "sim/system.hh" 4412966SMatteo.Andreozzi@arm.com 4512966SMatteo.Andreozzi@arm.comThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) 4612968Sgiacomo.travaglini@arm.com : numInst(0), numOp(0), numLoad(0), _status(ThreadContext::Halted), 4712968Sgiacomo.travaglini@arm.com baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0), 4812968Sgiacomo.travaglini@arm.com profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 4912968Sgiacomo.travaglini@arm.com kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL), 5012968Sgiacomo.travaglini@arm.com proxy(NULL), funcExeInst(0), storeCondFailures(0) 51{ 52} 53 54ThreadState::~ThreadState() 55{ 56 if (physProxy != NULL) 57 delete physProxy; 58 if (virtProxy != NULL) 59 delete virtProxy; 60 if (proxy != NULL) 61 delete proxy; 62} 63 64void 65ThreadState::serialize(std::ostream &os) 66{ 67 SERIALIZE_ENUM(_status); 68 // thread_num and cpu_id are deterministic from the config 69 SERIALIZE_SCALAR(funcExeInst); 70 71 if (!FullSystem) 72 return; 73 74 Tick quiesceEndTick = 0; 75 if (quiesceEvent->scheduled()) 76 quiesceEndTick = quiesceEvent->when(); 77 SERIALIZE_SCALAR(quiesceEndTick); 78 if (kernelStats) 79 kernelStats->serialize(os); 80} 81 82void 83ThreadState::unserialize(Checkpoint *cp, const std::string §ion) 84{ 85 86 UNSERIALIZE_ENUM(_status); 87 // thread_num and cpu_id are deterministic from the config 88 UNSERIALIZE_SCALAR(funcExeInst); 89 90 if (!FullSystem) 91 return; 92 93 Tick quiesceEndTick; 94 UNSERIALIZE_SCALAR(quiesceEndTick); 95 if (quiesceEndTick) 96 baseCpu->schedule(quiesceEvent, quiesceEndTick); 97 if (kernelStats) 98 kernelStats->unserialize(cp, section); 99} 100 101void 102ThreadState::initMemProxies(ThreadContext *tc) 103{ 104 // Note that this only refers to the port on the CPU side and can 105 // safely be done at init() time even if the CPU is not connected 106 // (i.e. due to restoring from a checkpoint and later switching 107 // in. 108 if (physProxy == NULL) 109 // this cannot be done in the constructor as the thread state 110 // itself is created in the base cpu constructor and the 111 // getPort is a virtual function at the moment 112 physProxy = new PortProxy(baseCpu->getDataPort()); 113 if (virtProxy == NULL) 114 virtProxy = new FSTranslatingPortProxy(tc); 115} 116 117void 118ThreadState::profileClear() 119{ 120 if (profile) 121 profile->clear(); 122} 123 124void 125ThreadState::profileSample() 126{ 127 if (profile) 128 profile->sample(profileNode, profilePC); 129} 130 131SETranslatingPortProxy & 132ThreadState::getMemProxy() 133{ 134 if (proxy == NULL) 135 proxy = new SETranslatingPortProxy(baseCpu->getDataPort(), 136 process, 137 SETranslatingPortProxy::NextPage); 138 return *proxy; 139} 140