thread_state.cc revision 5497
15353Svilas.sridharan@gmail.com/* 23395Shsul@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33395Shsul@eecs.umich.edu * All rights reserved. 43395Shsul@eecs.umich.edu * 53395Shsul@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu * modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu * this software without specific prior written permission. 153395Shsul@eecs.umich.edu * 163395Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu * 283395Shsul@eecs.umich.edu * Authors: Kevin Lim 293395Shsul@eecs.umich.edu */ 303395Shsul@eecs.umich.edu 313395Shsul@eecs.umich.edu#include "base/output.hh" 325869Sksewell@umich.edu#include "cpu/base.hh" 335361Srstrong@cs.ucsd.edu#include "cpu/profile.hh" 343395Shsul@eecs.umich.edu#include "cpu/thread_state.hh" 354455Ssaidi@eecs.umich.edu#include "mem/port.hh" 364968Sacolyte@umich.edu#include "mem/translating_port.hh" 373395Shsul@eecs.umich.edu#include "sim/serialize.hh" 383395Shsul@eecs.umich.edu 393395Shsul@eecs.umich.edu#if FULL_SYSTEM 403395Shsul@eecs.umich.edu#include "arch/kernel_stats.hh" 416641Sksewell@umich.edu#include "cpu/quiesce_event.hh" 426144Sksewell@umich.edu#include "mem/vport.hh" 436144Sksewell@umich.edu#endif 443395Shsul@eecs.umich.edu 453395Shsul@eecs.umich.edu#if FULL_SYSTEM 463395Shsul@eecs.umich.eduThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) 473395Shsul@eecs.umich.edu : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 485361Srstrong@cs.ucsd.edu profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), 495361Srstrong@cs.ucsd.edu kernelStats(NULL), physPort(NULL), virtPort(NULL), 505361Srstrong@cs.ucsd.edu microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 515361Srstrong@cs.ucsd.edu#else 525361Srstrong@cs.ucsd.eduThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, 535361Srstrong@cs.ucsd.edu short _asid) 545361Srstrong@cs.ucsd.edu : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), 555361Srstrong@cs.ucsd.edu port(NULL), process(_process), asid(_asid), 563395Shsul@eecs.umich.edu microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) 573395Shsul@eecs.umich.edu#endif 583395Shsul@eecs.umich.edu{ 593395Shsul@eecs.umich.edu numInst = 0; 605361Srstrong@cs.ucsd.edu numLoad = 0; 615361Srstrong@cs.ucsd.edu} 623445Shsul@eecs.umich.edu 635361Srstrong@cs.ucsd.eduThreadState::~ThreadState() 645361Srstrong@cs.ucsd.edu{ 656769SBrad.Beckmann@amd.com#if !FULL_SYSTEM 665361Srstrong@cs.ucsd.edu if (port) { 675361Srstrong@cs.ucsd.edu delete port->getPeer(); 685361Srstrong@cs.ucsd.edu delete port; 695361Srstrong@cs.ucsd.edu } 705361Srstrong@cs.ucsd.edu#endif 715361Srstrong@cs.ucsd.edu} 725361Srstrong@cs.ucsd.edu 735361Srstrong@cs.ucsd.eduvoid 745361Srstrong@cs.ucsd.eduThreadState::serialize(std::ostream &os) 755361Srstrong@cs.ucsd.edu{ 765361Srstrong@cs.ucsd.edu SERIALIZE_ENUM(_status); 775361Srstrong@cs.ucsd.edu // thread_num and cpu_id are deterministic from the config 785361Srstrong@cs.ucsd.edu SERIALIZE_SCALAR(funcExeInst); 795361Srstrong@cs.ucsd.edu SERIALIZE_SCALAR(inst); 805361Srstrong@cs.ucsd.edu SERIALIZE_SCALAR(microPC); 815361Srstrong@cs.ucsd.edu SERIALIZE_SCALAR(nextMicroPC); 825361Srstrong@cs.ucsd.edu 835361Srstrong@cs.ucsd.edu#if FULL_SYSTEM 84 Tick quiesceEndTick = 0; 85 if (quiesceEvent->scheduled()) 86 quiesceEndTick = quiesceEvent->when(); 87 SERIALIZE_SCALAR(quiesceEndTick); 88 if (kernelStats) 89 kernelStats->serialize(os); 90#endif 91} 92 93void 94ThreadState::unserialize(Checkpoint *cp, const std::string §ion) 95{ 96 97 UNSERIALIZE_ENUM(_status); 98 // thread_num and cpu_id are deterministic from the config 99 UNSERIALIZE_SCALAR(funcExeInst); 100 UNSERIALIZE_SCALAR(inst); 101 UNSERIALIZE_SCALAR(microPC); 102 UNSERIALIZE_SCALAR(nextMicroPC); 103 104#if FULL_SYSTEM 105 Tick quiesceEndTick; 106 UNSERIALIZE_SCALAR(quiesceEndTick); 107 if (quiesceEndTick) 108 quiesceEvent->schedule(quiesceEndTick); 109 if (kernelStats) 110 kernelStats->unserialize(cp, section); 111#endif 112} 113 114#if FULL_SYSTEM 115void 116ThreadState::connectMemPorts(ThreadContext *tc) 117{ 118 connectPhysPort(); 119 connectVirtPort(tc); 120} 121 122void 123ThreadState::connectPhysPort() 124{ 125 // @todo: For now this disregards any older port that may have 126 // already existed. Fix this memory leak once the bus port IDs 127 // for functional ports is resolved. 128 if (physPort) 129 physPort->removeConn(); 130 else 131 physPort = new FunctionalPort(csprintf("%s-%d-funcport", 132 baseCpu->name(), tid)); 133 connectToMemFunc(physPort); 134} 135 136void 137ThreadState::connectVirtPort(ThreadContext *tc) 138{ 139 // @todo: For now this disregards any older port that may have 140 // already existed. Fix this memory leak once the bus port IDs 141 // for functional ports is resolved. 142 if (virtPort) 143 virtPort->removeConn(); 144 else 145 virtPort = new VirtualPort(csprintf("%s-%d-vport", 146 baseCpu->name(), tid), tc); 147 connectToMemFunc(virtPort); 148} 149 150void 151ThreadState::profileClear() 152{ 153 if (profile) 154 profile->clear(); 155} 156 157void 158ThreadState::profileSample() 159{ 160 if (profile) 161 profile->sample(profileNode, profilePC); 162} 163 164#else 165TranslatingPort * 166ThreadState::getMemPort() 167{ 168 if (port != NULL) 169 return port; 170 171 /* Use this port to for syscall emulation writes to memory. */ 172 port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid), 173 process, TranslatingPort::NextPage); 174 175 connectToMemFunc(port); 176 177 return port; 178} 179#endif 180 181void 182ThreadState::connectToMemFunc(Port *port) 183{ 184 Port *dcache_port, *func_mem_port; 185 186 dcache_port = baseCpu->getPort("dcache_port"); 187 assert(dcache_port != NULL); 188 189 MemObject *mem_object = dcache_port->getPeer()->getOwner(); 190 assert(mem_object != NULL); 191 192 func_mem_port = mem_object->getPort("functional"); 193 assert(func_mem_port != NULL); 194 195 func_mem_port->setPeer(port); 196 port->setPeer(func_mem_port); 197} 198