thread_state.cc revision 3675 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "base/output.hh"
32#include "cpu/base.hh"
33#include "cpu/profile.hh"
34#include "cpu/thread_state.hh"
35#include "mem/port.hh"
36#include "mem/translating_port.hh"
37#include "sim/serialize.hh"
38
39#if FULL_SYSTEM
40#include "arch/kernel_stats.hh"
41#include "cpu/quiesce_event.hh"
42#include "mem/vport.hh"
43#endif
44
45#if FULL_SYSTEM
46ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid)
47    : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
48      profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
49      physPort(NULL), virtPort(NULL),
50      microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
51#else
52ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
53                         short _asid)
54    : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
55      port(NULL), process(_process), asid(_asid),
56      microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
57#endif
58{
59    numInst = 0;
60    numLoad = 0;
61}
62
63ThreadState::~ThreadState()
64{
65#if !FULL_SYSTEM
66    if (port) {
67        delete port->getPeer();
68        delete port;
69    }
70#endif
71}
72
73void
74ThreadState::serialize(std::ostream &os)
75{
76    SERIALIZE_ENUM(_status);
77    // thread_num and cpu_id are deterministic from the config
78    SERIALIZE_SCALAR(funcExeInst);
79    SERIALIZE_SCALAR(inst);
80    SERIALIZE_SCALAR(microPC);
81    SERIALIZE_SCALAR(nextMicroPC);
82
83#if FULL_SYSTEM
84    Tick quiesceEndTick = 0;
85    if (quiesceEvent->scheduled())
86        quiesceEndTick = quiesceEvent->when();
87    SERIALIZE_SCALAR(quiesceEndTick);
88    if (kernelStats)
89        kernelStats->serialize(os);
90#endif
91}
92
93void
94ThreadState::unserialize(Checkpoint *cp, const std::string &section)
95{
96
97    UNSERIALIZE_ENUM(_status);
98    // thread_num and cpu_id are deterministic from the config
99    UNSERIALIZE_SCALAR(funcExeInst);
100    UNSERIALIZE_SCALAR(inst);
101    UNSERIALIZE_SCALAR(microPC);
102    UNSERIALIZE_SCALAR(nextMicroPC);
103
104#if FULL_SYSTEM
105    Tick quiesceEndTick;
106    UNSERIALIZE_SCALAR(quiesceEndTick);
107    if (quiesceEndTick)
108        quiesceEvent->schedule(quiesceEndTick);
109    if (kernelStats)
110        kernelStats->unserialize(cp, section);
111#endif
112}
113
114#if FULL_SYSTEM
115void
116ThreadState::init()
117{
118    initPhysPort();
119    initVirtPort();
120}
121
122void
123ThreadState::initPhysPort()
124{
125    physPort = new FunctionalPort(csprintf("%s-%d-funcport",
126                                           baseCpu->name(), tid));
127    connectToMemFunc(physPort);
128}
129
130void
131ThreadState::initVirtPort()
132{
133    virtPort = new VirtualPort(csprintf("%s-%d-vport",
134                                        baseCpu->name(), tid));
135    connectToMemFunc(virtPort);
136}
137
138void
139ThreadState::profileClear()
140{
141    if (profile)
142        profile->clear();
143}
144
145void
146ThreadState::profileSample()
147{
148    if (profile)
149        profile->sample(profileNode, profilePC);
150}
151
152#else
153TranslatingPort *
154ThreadState::getMemPort()
155{
156    if (port != NULL)
157        return port;
158
159    /* Use this port to for syscall emulation writes to memory. */
160    port = new TranslatingPort(csprintf("%s-%d-funcport",
161                                        baseCpu->name(), tid),
162                               process->pTable, false);
163
164    connectToMemFunc(port);
165
166    return port;
167}
168#endif
169
170void
171ThreadState::connectToMemFunc(Port *port)
172{
173    Port *dcache_port, *func_mem_port;
174
175    dcache_port = baseCpu->getPort("dcache_port");
176    assert(dcache_port != NULL);
177
178    MemObject *mem_object = dcache_port->getPeer()->getOwner();
179    assert(mem_object != NULL);
180
181    func_mem_port = mem_object->getPort("functional");
182    assert(func_mem_port != NULL);
183
184    func_mem_port->setPeer(port);
185    port->setPeer(func_mem_port);
186}
187