thread_context.hh revision 9441
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_THREAD_CONTEXT_HH__ 44#define __CPU_THREAD_CONTEXT_HH__ 45 46#include <iostream> 47#include <string> 48 49#include "arch/registers.hh" 50#include "arch/types.hh" 51#include "base/types.hh" 52#include "config/the_isa.hh" 53 54// @todo: Figure out a more architecture independent way to obtain the ITB and 55// DTB pointers. 56namespace TheISA 57{ 58 class Decoder; 59 class TLB; 60} 61class BaseCPU; 62class CheckerCPU; 63class Checkpoint; 64class EndQuiesceEvent; 65class SETranslatingPortProxy; 66class FSTranslatingPortProxy; 67class PortProxy; 68class Process; 69class System; 70namespace TheISA { 71 namespace Kernel { 72 class Statistics; 73 } 74} 75 76/** 77 * ThreadContext is the external interface to all thread state for 78 * anything outside of the CPU. It provides all accessor methods to 79 * state that might be needed by external objects, ranging from 80 * register values to things such as kernel stats. It is an abstract 81 * base class; the CPU can create its own ThreadContext by either 82 * deriving from it, or using the templated ProxyThreadContext. 83 * 84 * The ThreadContext is slightly different than the ExecContext. The 85 * ThreadContext provides access to an individual thread's state; an 86 * ExecContext provides ISA access to the CPU (meaning it is 87 * implicitly multithreaded on SMT systems). Additionally the 88 * ThreadState is an abstract class that exactly defines the 89 * interface; the ExecContext is a more implicit interface that must 90 * be implemented so that the ISA can access whatever state it needs. 91 */ 92class ThreadContext 93{ 94 protected: 95 typedef TheISA::MachInst MachInst; 96 typedef TheISA::IntReg IntReg; 97 typedef TheISA::FloatReg FloatReg; 98 typedef TheISA::FloatRegBits FloatRegBits; 99 typedef TheISA::MiscReg MiscReg; 100 public: 101 102 enum Status 103 { 104 /// Running. Instructions should be executed only when 105 /// the context is in this state. 106 Active, 107 108 /// Temporarily inactive. Entered while waiting for 109 /// synchronization, etc. 110 Suspended, 111 112 /// Permanently shut down. Entered when target executes 113 /// m5exit pseudo-instruction. When all contexts enter 114 /// this state, the simulation will terminate. 115 Halted 116 }; 117 118 virtual ~ThreadContext() { }; 119 120 virtual BaseCPU *getCpuPtr() = 0; 121 122 virtual int cpuId() = 0; 123 124 virtual int threadId() = 0; 125 126 virtual void setThreadId(int id) = 0; 127 128 virtual int contextId() = 0; 129 130 virtual void setContextId(int id) = 0; 131 132 virtual TheISA::TLB *getITBPtr() = 0; 133 134 virtual TheISA::TLB *getDTBPtr() = 0; 135 136 virtual CheckerCPU *getCheckerCpuPtr() = 0; 137 138 virtual TheISA::Decoder *getDecoderPtr() = 0; 139 140 virtual System *getSystemPtr() = 0; 141 142 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 143 144 virtual PortProxy &getPhysProxy() = 0; 145 146 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 147 148 /** 149 * Initialise the physical and virtual port proxies and tie them to 150 * the data port of the CPU. 151 * 152 * tc ThreadContext for the virtual-to-physical translation 153 */ 154 virtual void initMemProxies(ThreadContext *tc) = 0; 155 156 virtual SETranslatingPortProxy &getMemProxy() = 0; 157 158 virtual Process *getProcessPtr() = 0; 159 160 virtual Status status() const = 0; 161 162 virtual void setStatus(Status new_status) = 0; 163 164 /// Set the status to Active. Optional delay indicates number of 165 /// cycles to wait before beginning execution. 166 virtual void activate(Cycles delay = Cycles(1)) = 0; 167 168 /// Set the status to Suspended. 169 virtual void suspend(Cycles delay = Cycles(0)) = 0; 170 171 /// Set the status to Halted. 172 virtual void halt(Cycles delay = Cycles(0)) = 0; 173 174 virtual void dumpFuncProfile() = 0; 175 176 virtual void takeOverFrom(ThreadContext *old_context) = 0; 177 178 virtual void regStats(const std::string &name) = 0; 179 180 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 181 182 // Not necessarily the best location for these... 183 // Having an extra function just to read these is obnoxious 184 virtual Tick readLastActivate() = 0; 185 virtual Tick readLastSuspend() = 0; 186 187 virtual void profileClear() = 0; 188 virtual void profileSample() = 0; 189 190 virtual void copyArchRegs(ThreadContext *tc) = 0; 191 192 virtual void clearArchRegs() = 0; 193 194 // 195 // New accessors for new decoder. 196 // 197 virtual uint64_t readIntReg(int reg_idx) = 0; 198 199 virtual FloatReg readFloatReg(int reg_idx) = 0; 200 201 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 202 203 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 204 205 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 206 207 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 208 209 virtual TheISA::PCState pcState() = 0; 210 211 virtual void pcState(const TheISA::PCState &val) = 0; 212 213 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 214 215 virtual Addr instAddr() = 0; 216 217 virtual Addr nextInstAddr() = 0; 218 219 virtual MicroPC microPC() = 0; 220 221 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 222 223 virtual MiscReg readMiscReg(int misc_reg) = 0; 224 225 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 226 227 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 228 229 virtual int flattenIntIndex(int reg) = 0; 230 virtual int flattenFloatIndex(int reg) = 0; 231 232 virtual uint64_t 233 readRegOtherThread(int misc_reg, ThreadID tid) 234 { 235 return 0; 236 } 237 238 virtual void 239 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 240 { 241 } 242 243 // Also not necessarily the best location for these two. Hopefully will go 244 // away once we decide upon where st cond failures goes. 245 virtual unsigned readStCondFailures() = 0; 246 247 virtual void setStCondFailures(unsigned sc_failures) = 0; 248 249 // Only really makes sense for old CPU model. Still could be useful though. 250 virtual bool misspeculating() = 0; 251 252 // Same with st cond failures. 253 virtual Counter readFuncExeInst() = 0; 254 255 virtual void syscall(int64_t callnum) = 0; 256 257 // This function exits the thread context in the CPU and returns 258 // 1 if the CPU has no more active threads (meaning it's OK to exit); 259 // Used in syscall-emulation mode when a thread calls the exit syscall. 260 virtual int exit() { return 1; }; 261 262 /** function to compare two thread contexts (for debugging) */ 263 static void compare(ThreadContext *one, ThreadContext *two); 264 265 /** @{ */ 266 /** 267 * Flat register interfaces 268 * 269 * Some architectures have different registers visible in 270 * different modes. Such architectures "flatten" a register (see 271 * flattenIntIndex() and flattenFloatIndex()) to map it into the 272 * gem5 register file. This interface provides a flat interface to 273 * the underlying register file, which allows for example 274 * serialization code to access all registers. 275 */ 276 277 virtual uint64_t readIntRegFlat(int idx) = 0; 278 virtual void setIntRegFlat(int idx, uint64_t val) = 0; 279 280 virtual FloatReg readFloatRegFlat(int idx) = 0; 281 virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 282 283 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 284 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 285 286 /** @} */ 287 288}; 289 290/** 291 * ProxyThreadContext class that provides a way to implement a 292 * ThreadContext without having to derive from it. ThreadContext is an 293 * abstract class, so anything that derives from it and uses its 294 * interface will pay the overhead of virtual function calls. This 295 * class is created to enable a user-defined Thread object to be used 296 * wherever ThreadContexts are used, without paying the overhead of 297 * virtual function calls when it is used by itself. See 298 * simple_thread.hh for an example of this. 299 */ 300template <class TC> 301class ProxyThreadContext : public ThreadContext 302{ 303 public: 304 ProxyThreadContext(TC *actual_tc) 305 { actualTC = actual_tc; } 306 307 private: 308 TC *actualTC; 309 310 public: 311 312 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 313 314 int cpuId() { return actualTC->cpuId(); } 315 316 int threadId() { return actualTC->threadId(); } 317 318 void setThreadId(int id) { return actualTC->setThreadId(id); } 319 320 int contextId() { return actualTC->contextId(); } 321 322 void setContextId(int id) { actualTC->setContextId(id); } 323 324 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 325 326 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 327 328 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 329 330 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 331 332 System *getSystemPtr() { return actualTC->getSystemPtr(); } 333 334 TheISA::Kernel::Statistics *getKernelStats() 335 { return actualTC->getKernelStats(); } 336 337 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 338 339 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 340 341 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 342 343 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 344 345 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 346 347 Status status() const { return actualTC->status(); } 348 349 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 350 351 /// Set the status to Active. Optional delay indicates number of 352 /// cycles to wait before beginning execution. 353 void activate(Cycles delay = Cycles(1)) 354 { actualTC->activate(delay); } 355 356 /// Set the status to Suspended. 357 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 358 359 /// Set the status to Halted. 360 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 361 362 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 363 364 void takeOverFrom(ThreadContext *oldContext) 365 { actualTC->takeOverFrom(oldContext); } 366 367 void regStats(const std::string &name) { actualTC->regStats(name); } 368 369 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 370 371 Tick readLastActivate() { return actualTC->readLastActivate(); } 372 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 373 374 void profileClear() { return actualTC->profileClear(); } 375 void profileSample() { return actualTC->profileSample(); } 376 377 // @todo: Do I need this? 378 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 379 380 void clearArchRegs() { actualTC->clearArchRegs(); } 381 382 // 383 // New accessors for new decoder. 384 // 385 uint64_t readIntReg(int reg_idx) 386 { return actualTC->readIntReg(reg_idx); } 387 388 FloatReg readFloatReg(int reg_idx) 389 { return actualTC->readFloatReg(reg_idx); } 390 391 FloatRegBits readFloatRegBits(int reg_idx) 392 { return actualTC->readFloatRegBits(reg_idx); } 393 394 void setIntReg(int reg_idx, uint64_t val) 395 { actualTC->setIntReg(reg_idx, val); } 396 397 void setFloatReg(int reg_idx, FloatReg val) 398 { actualTC->setFloatReg(reg_idx, val); } 399 400 void setFloatRegBits(int reg_idx, FloatRegBits val) 401 { actualTC->setFloatRegBits(reg_idx, val); } 402 403 TheISA::PCState pcState() { return actualTC->pcState(); } 404 405 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 406 407 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 408 409 Addr instAddr() { return actualTC->instAddr(); } 410 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 411 MicroPC microPC() { return actualTC->microPC(); } 412 413 bool readPredicate() { return actualTC->readPredicate(); } 414 415 void setPredicate(bool val) 416 { actualTC->setPredicate(val); } 417 418 MiscReg readMiscRegNoEffect(int misc_reg) 419 { return actualTC->readMiscRegNoEffect(misc_reg); } 420 421 MiscReg readMiscReg(int misc_reg) 422 { return actualTC->readMiscReg(misc_reg); } 423 424 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 425 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 426 427 void setMiscReg(int misc_reg, const MiscReg &val) 428 { return actualTC->setMiscReg(misc_reg, val); } 429 430 int flattenIntIndex(int reg) 431 { return actualTC->flattenIntIndex(reg); } 432 433 int flattenFloatIndex(int reg) 434 { return actualTC->flattenFloatIndex(reg); } 435 436 unsigned readStCondFailures() 437 { return actualTC->readStCondFailures(); } 438 439 void setStCondFailures(unsigned sc_failures) 440 { actualTC->setStCondFailures(sc_failures); } 441 442 // @todo: Fix this! 443 bool misspeculating() { return actualTC->misspeculating(); } 444 445 void syscall(int64_t callnum) 446 { actualTC->syscall(callnum); } 447 448 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 449 450 uint64_t readIntRegFlat(int idx) 451 { return actualTC->readIntRegFlat(idx); } 452 453 void setIntRegFlat(int idx, uint64_t val) 454 { actualTC->setIntRegFlat(idx, val); } 455 456 FloatReg readFloatRegFlat(int idx) 457 { return actualTC->readFloatRegFlat(idx); } 458 459 void setFloatRegFlat(int idx, FloatReg val) 460 { actualTC->setFloatRegFlat(idx, val); } 461 462 FloatRegBits readFloatRegBitsFlat(int idx) 463 { return actualTC->readFloatRegBitsFlat(idx); } 464 465 void setFloatRegBitsFlat(int idx, FloatRegBits val) 466 { actualTC->setFloatRegBitsFlat(idx, val); } 467}; 468 469/** @{ */ 470/** 471 * Thread context serialization helpers 472 * 473 * These helper functions provide a way to the data in a 474 * ThreadContext. They are provided as separate helper function since 475 * implementing them as members of the ThreadContext interface would 476 * be confusing when the ThreadContext is exported via a proxy. 477 */ 478 479void serialize(ThreadContext &tc, std::ostream &os); 480void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 481 482/** @} */ 483 484 485/** 486 * Copy state between thread contexts in preparation for CPU handover. 487 * 488 * @note This method modifies the old thread contexts as well as the 489 * new thread context. The old thread context will have its quiesce 490 * event descheduled if it is scheduled and its status set to halted. 491 * 492 * @param new_tc Destination ThreadContext. 493 * @param old_tc Source ThreadContext. 494 */ 495void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 496 497#endif 498