thread_context.hh revision 9180
15325Sgblack@eecs.umich.edu/*
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395149Sgblack@eecs.umich.edu *
405149Sgblack@eecs.umich.edu * Authors: Kevin Lim
415149Sgblack@eecs.umich.edu */
425149Sgblack@eecs.umich.edu
435149Sgblack@eecs.umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__
445149Sgblack@eecs.umich.edu#define __CPU_THREAD_CONTEXT_HH__
455149Sgblack@eecs.umich.edu
465149Sgblack@eecs.umich.edu#include <iostream>
475149Sgblack@eecs.umich.edu#include <string>
485149Sgblack@eecs.umich.edu
495149Sgblack@eecs.umich.edu#include "arch/registers.hh"
505149Sgblack@eecs.umich.edu#include "arch/types.hh"
515149Sgblack@eecs.umich.edu#include "base/types.hh"
525149Sgblack@eecs.umich.edu#include "config/the_isa.hh"
535149Sgblack@eecs.umich.edu
545149Sgblack@eecs.umich.edu// @todo: Figure out a more architecture independent way to obtain the ITB and
555149Sgblack@eecs.umich.edu// DTB pointers.
565149Sgblack@eecs.umich.edunamespace TheISA
575149Sgblack@eecs.umich.edu{
585149Sgblack@eecs.umich.edu    class Decoder;
595149Sgblack@eecs.umich.edu    class TLB;
605149Sgblack@eecs.umich.edu}
615149Sgblack@eecs.umich.educlass BaseCPU;
625149Sgblack@eecs.umich.educlass CheckerCPU;
635149Sgblack@eecs.umich.educlass Checkpoint;
645149Sgblack@eecs.umich.educlass EndQuiesceEvent;
655149Sgblack@eecs.umich.educlass SETranslatingPortProxy;
665149Sgblack@eecs.umich.educlass FSTranslatingPortProxy;
675149Sgblack@eecs.umich.educlass PortProxy;
685149Sgblack@eecs.umich.educlass Process;
695149Sgblack@eecs.umich.educlass System;
705149Sgblack@eecs.umich.edunamespace TheISA {
715149Sgblack@eecs.umich.edu    namespace Kernel {
725149Sgblack@eecs.umich.edu        class Statistics;
735149Sgblack@eecs.umich.edu    }
745149Sgblack@eecs.umich.edu}
755149Sgblack@eecs.umich.edu
765149Sgblack@eecs.umich.edu/**
775149Sgblack@eecs.umich.edu * ThreadContext is the external interface to all thread state for
785149Sgblack@eecs.umich.edu * anything outside of the CPU. It provides all accessor methods to
795149Sgblack@eecs.umich.edu * state that might be needed by external objects, ranging from
805149Sgblack@eecs.umich.edu * register values to things such as kernel stats. It is an abstract
815149Sgblack@eecs.umich.edu * base class; the CPU can create its own ThreadContext by either
825149Sgblack@eecs.umich.edu * deriving from it, or using the templated ProxyThreadContext.
835149Sgblack@eecs.umich.edu *
845149Sgblack@eecs.umich.edu * The ThreadContext is slightly different than the ExecContext.  The
855243Sgblack@eecs.umich.edu * ThreadContext provides access to an individual thread's state; an
865149Sgblack@eecs.umich.edu * ExecContext provides ISA access to the CPU (meaning it is
875149Sgblack@eecs.umich.edu * implicitly multithreaded on SMT systems).  Additionally the
885149Sgblack@eecs.umich.edu * ThreadState is an abstract class that exactly defines the
895149Sgblack@eecs.umich.edu * interface; the ExecContext is a more implicit interface that must
905149Sgblack@eecs.umich.edu * be implemented so that the ISA can access whatever state it needs.
915149Sgblack@eecs.umich.edu */
925149Sgblack@eecs.umich.educlass ThreadContext
935149Sgblack@eecs.umich.edu{
945243Sgblack@eecs.umich.edu  protected:
955149Sgblack@eecs.umich.edu    typedef TheISA::MachInst MachInst;
965149Sgblack@eecs.umich.edu    typedef TheISA::IntReg IntReg;
975149Sgblack@eecs.umich.edu    typedef TheISA::FloatReg FloatReg;
985325Sgblack@eecs.umich.edu    typedef TheISA::FloatRegBits FloatRegBits;
995325Sgblack@eecs.umich.edu    typedef TheISA::MiscReg MiscReg;
1005149Sgblack@eecs.umich.edu  public:
1015149Sgblack@eecs.umich.edu
1025409Sgblack@eecs.umich.edu    enum Status
1035409Sgblack@eecs.umich.edu    {
1045409Sgblack@eecs.umich.edu        /// Running.  Instructions should be executed only when
1055409Sgblack@eecs.umich.edu        /// the context is in this state.
1065409Sgblack@eecs.umich.edu        Active,
1075409Sgblack@eecs.umich.edu
1085409Sgblack@eecs.umich.edu        /// Temporarily inactive.  Entered while waiting for
1095409Sgblack@eecs.umich.edu        /// synchronization, etc.
1105149Sgblack@eecs.umich.edu        Suspended,
111
112        /// Permanently shut down.  Entered when target executes
113        /// m5exit pseudo-instruction.  When all contexts enter
114        /// this state, the simulation will terminate.
115        Halted
116    };
117
118    virtual ~ThreadContext() { };
119
120    virtual BaseCPU *getCpuPtr() = 0;
121
122    virtual int cpuId() = 0;
123
124    virtual int threadId() = 0;
125
126    virtual void setThreadId(int id) = 0;
127
128    virtual int contextId() = 0;
129
130    virtual void setContextId(int id) = 0;
131
132    virtual TheISA::TLB *getITBPtr() = 0;
133
134    virtual TheISA::TLB *getDTBPtr() = 0;
135
136    virtual CheckerCPU *getCheckerCpuPtr() = 0;
137
138    virtual TheISA::Decoder *getDecoderPtr() = 0;
139
140    virtual System *getSystemPtr() = 0;
141
142    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
143
144    virtual PortProxy &getPhysProxy() = 0;
145
146    virtual FSTranslatingPortProxy &getVirtProxy() = 0;
147
148    /**
149     * Initialise the physical and virtual port proxies and tie them to
150     * the data port of the CPU.
151     *
152     * tc ThreadContext for the virtual-to-physical translation
153     */
154    virtual void initMemProxies(ThreadContext *tc) = 0;
155
156    virtual SETranslatingPortProxy &getMemProxy() = 0;
157
158    virtual Process *getProcessPtr() = 0;
159
160    virtual Status status() const = 0;
161
162    virtual void setStatus(Status new_status) = 0;
163
164    /// Set the status to Active.  Optional delay indicates number of
165    /// cycles to wait before beginning execution.
166    virtual void activate(Cycles delay = Cycles(1)) = 0;
167
168    /// Set the status to Suspended.
169    virtual void suspend(Cycles delay = Cycles(0)) = 0;
170
171    /// Set the status to Halted.
172    virtual void halt(Cycles delay = Cycles(0)) = 0;
173
174    virtual void dumpFuncProfile() = 0;
175
176    virtual void takeOverFrom(ThreadContext *old_context) = 0;
177
178    virtual void regStats(const std::string &name) = 0;
179
180    virtual void serialize(std::ostream &os) = 0;
181    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
182
183    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
184
185    // Not necessarily the best location for these...
186    // Having an extra function just to read these is obnoxious
187    virtual Tick readLastActivate() = 0;
188    virtual Tick readLastSuspend() = 0;
189
190    virtual void profileClear() = 0;
191    virtual void profileSample() = 0;
192
193    virtual void copyArchRegs(ThreadContext *tc) = 0;
194
195    virtual void clearArchRegs() = 0;
196
197    //
198    // New accessors for new decoder.
199    //
200    virtual uint64_t readIntReg(int reg_idx) = 0;
201
202    virtual FloatReg readFloatReg(int reg_idx) = 0;
203
204    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
205
206    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
207
208    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
209
210    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
211
212    virtual TheISA::PCState pcState() = 0;
213
214    virtual void pcState(const TheISA::PCState &val) = 0;
215
216    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
217
218    virtual Addr instAddr() = 0;
219
220    virtual Addr nextInstAddr() = 0;
221
222    virtual MicroPC microPC() = 0;
223
224    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
225
226    virtual MiscReg readMiscReg(int misc_reg) = 0;
227
228    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
229
230    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
231
232    virtual int flattenIntIndex(int reg) = 0;
233    virtual int flattenFloatIndex(int reg) = 0;
234
235    virtual uint64_t
236    readRegOtherThread(int misc_reg, ThreadID tid)
237    {
238        return 0;
239    }
240
241    virtual void
242    setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
243    {
244    }
245
246    // Also not necessarily the best location for these two.  Hopefully will go
247    // away once we decide upon where st cond failures goes.
248    virtual unsigned readStCondFailures() = 0;
249
250    virtual void setStCondFailures(unsigned sc_failures) = 0;
251
252    // Only really makes sense for old CPU model.  Still could be useful though.
253    virtual bool misspeculating() = 0;
254
255    // Same with st cond failures.
256    virtual Counter readFuncExeInst() = 0;
257
258    virtual void syscall(int64_t callnum) = 0;
259
260    // This function exits the thread context in the CPU and returns
261    // 1 if the CPU has no more active threads (meaning it's OK to exit);
262    // Used in syscall-emulation mode when a  thread calls the exit syscall.
263    virtual int exit() { return 1; };
264
265    /** function to compare two thread contexts (for debugging) */
266    static void compare(ThreadContext *one, ThreadContext *two);
267};
268
269/**
270 * ProxyThreadContext class that provides a way to implement a
271 * ThreadContext without having to derive from it. ThreadContext is an
272 * abstract class, so anything that derives from it and uses its
273 * interface will pay the overhead of virtual function calls.  This
274 * class is created to enable a user-defined Thread object to be used
275 * wherever ThreadContexts are used, without paying the overhead of
276 * virtual function calls when it is used by itself.  See
277 * simple_thread.hh for an example of this.
278 */
279template <class TC>
280class ProxyThreadContext : public ThreadContext
281{
282  public:
283    ProxyThreadContext(TC *actual_tc)
284    { actualTC = actual_tc; }
285
286  private:
287    TC *actualTC;
288
289  public:
290
291    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
292
293    int cpuId() { return actualTC->cpuId(); }
294
295    int threadId() { return actualTC->threadId(); }
296
297    void setThreadId(int id) { return actualTC->setThreadId(id); }
298
299    int contextId() { return actualTC->contextId(); }
300
301    void setContextId(int id) { actualTC->setContextId(id); }
302
303    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
304
305    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
306
307    CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
308
309    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
310
311    System *getSystemPtr() { return actualTC->getSystemPtr(); }
312
313    TheISA::Kernel::Statistics *getKernelStats()
314    { return actualTC->getKernelStats(); }
315
316    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
317
318    FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
319
320    void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
321
322    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
323
324    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
325
326    Status status() const { return actualTC->status(); }
327
328    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
329
330    /// Set the status to Active.  Optional delay indicates number of
331    /// cycles to wait before beginning execution.
332    void activate(Cycles delay = Cycles(1))
333    { actualTC->activate(delay); }
334
335    /// Set the status to Suspended.
336    void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); }
337
338    /// Set the status to Halted.
339    void halt(Cycles delay = Cycles(0)) { actualTC->halt(); }
340
341    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
342
343    void takeOverFrom(ThreadContext *oldContext)
344    { actualTC->takeOverFrom(oldContext); }
345
346    void regStats(const std::string &name) { actualTC->regStats(name); }
347
348    void serialize(std::ostream &os) { actualTC->serialize(os); }
349    void unserialize(Checkpoint *cp, const std::string &section)
350    { actualTC->unserialize(cp, section); }
351
352    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
353
354    Tick readLastActivate() { return actualTC->readLastActivate(); }
355    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
356
357    void profileClear() { return actualTC->profileClear(); }
358    void profileSample() { return actualTC->profileSample(); }
359
360    // @todo: Do I need this?
361    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
362
363    void clearArchRegs() { actualTC->clearArchRegs(); }
364
365    //
366    // New accessors for new decoder.
367    //
368    uint64_t readIntReg(int reg_idx)
369    { return actualTC->readIntReg(reg_idx); }
370
371    FloatReg readFloatReg(int reg_idx)
372    { return actualTC->readFloatReg(reg_idx); }
373
374    FloatRegBits readFloatRegBits(int reg_idx)
375    { return actualTC->readFloatRegBits(reg_idx); }
376
377    void setIntReg(int reg_idx, uint64_t val)
378    { actualTC->setIntReg(reg_idx, val); }
379
380    void setFloatReg(int reg_idx, FloatReg val)
381    { actualTC->setFloatReg(reg_idx, val); }
382
383    void setFloatRegBits(int reg_idx, FloatRegBits val)
384    { actualTC->setFloatRegBits(reg_idx, val); }
385
386    TheISA::PCState pcState() { return actualTC->pcState(); }
387
388    void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
389
390    void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
391
392    Addr instAddr() { return actualTC->instAddr(); }
393    Addr nextInstAddr() { return actualTC->nextInstAddr(); }
394    MicroPC microPC() { return actualTC->microPC(); }
395
396    bool readPredicate() { return actualTC->readPredicate(); }
397
398    void setPredicate(bool val)
399    { actualTC->setPredicate(val); }
400
401    MiscReg readMiscRegNoEffect(int misc_reg)
402    { return actualTC->readMiscRegNoEffect(misc_reg); }
403
404    MiscReg readMiscReg(int misc_reg)
405    { return actualTC->readMiscReg(misc_reg); }
406
407    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
408    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
409
410    void setMiscReg(int misc_reg, const MiscReg &val)
411    { return actualTC->setMiscReg(misc_reg, val); }
412
413    int flattenIntIndex(int reg)
414    { return actualTC->flattenIntIndex(reg); }
415
416    int flattenFloatIndex(int reg)
417    { return actualTC->flattenFloatIndex(reg); }
418
419    unsigned readStCondFailures()
420    { return actualTC->readStCondFailures(); }
421
422    void setStCondFailures(unsigned sc_failures)
423    { actualTC->setStCondFailures(sc_failures); }
424
425    // @todo: Fix this!
426    bool misspeculating() { return actualTC->misspeculating(); }
427
428    void syscall(int64_t callnum)
429    { actualTC->syscall(callnum); }
430
431    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
432};
433
434#endif
435