thread_context.hh revision 8733:64a7bf8fa56c
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_THREAD_CONTEXT_HH__ 44#define __CPU_THREAD_CONTEXT_HH__ 45 46#include <iostream> 47#include <string> 48 49#include "arch/registers.hh" 50#include "arch/types.hh" 51#include "base/types.hh" 52#include "config/full_system.hh" 53#include "config/the_isa.hh" 54#include "config/use_checker.hh" 55 56// @todo: Figure out a more architecture independent way to obtain the ITB and 57// DTB pointers. 58namespace TheISA 59{ 60 class TLB; 61} 62class BaseCPU; 63class Checkpoint; 64class Decoder; 65class EndQuiesceEvent; 66class SETranslatingPortProxy; 67class FSTranslatingPortProxy; 68class PortProxy; 69class Process; 70class System; 71namespace TheISA { 72 namespace Kernel { 73 class Statistics; 74 }; 75}; 76 77/** 78 * ThreadContext is the external interface to all thread state for 79 * anything outside of the CPU. It provides all accessor methods to 80 * state that might be needed by external objects, ranging from 81 * register values to things such as kernel stats. It is an abstract 82 * base class; the CPU can create its own ThreadContext by either 83 * deriving from it, or using the templated ProxyThreadContext. 84 * 85 * The ThreadContext is slightly different than the ExecContext. The 86 * ThreadContext provides access to an individual thread's state; an 87 * ExecContext provides ISA access to the CPU (meaning it is 88 * implicitly multithreaded on SMT systems). Additionally the 89 * ThreadState is an abstract class that exactly defines the 90 * interface; the ExecContext is a more implicit interface that must 91 * be implemented so that the ISA can access whatever state it needs. 92 */ 93class ThreadContext 94{ 95 protected: 96 typedef TheISA::MachInst MachInst; 97 typedef TheISA::IntReg IntReg; 98 typedef TheISA::FloatReg FloatReg; 99 typedef TheISA::FloatRegBits FloatRegBits; 100 typedef TheISA::MiscReg MiscReg; 101 public: 102 103 enum Status 104 { 105 /// Running. Instructions should be executed only when 106 /// the context is in this state. 107 Active, 108 109 /// Temporarily inactive. Entered while waiting for 110 /// synchronization, etc. 111 Suspended, 112 113 /// Permanently shut down. Entered when target executes 114 /// m5exit pseudo-instruction. When all contexts enter 115 /// this state, the simulation will terminate. 116 Halted 117 }; 118 119 virtual ~ThreadContext() { }; 120 121 virtual BaseCPU *getCpuPtr() = 0; 122 123 virtual int cpuId() = 0; 124 125 virtual int threadId() = 0; 126 127 virtual void setThreadId(int id) = 0; 128 129 virtual int contextId() = 0; 130 131 virtual void setContextId(int id) = 0; 132 133 virtual TheISA::TLB *getITBPtr() = 0; 134 135 virtual TheISA::TLB *getDTBPtr() = 0; 136 137#if USE_CHECKER 138 virtual BaseCPU *getCheckerCpuPtr() = 0; 139#endif 140 141 virtual Decoder *getDecoderPtr() = 0; 142 143 virtual System *getSystemPtr() = 0; 144 145#if FULL_SYSTEM 146 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 147 148 virtual PortProxy* getPhysProxy() = 0; 149 150 virtual FSTranslatingPortProxy* getVirtProxy() = 0; 151 152 /** 153 * Initialise the physical and virtual port proxies and tie them to 154 * the data port of the CPU. 155 * 156 * tc ThreadContext for the virtual-to-physical translation 157 */ 158 virtual void initMemProxies(ThreadContext *tc) = 0; 159#else 160 virtual SETranslatingPortProxy *getMemProxy() = 0; 161 162 virtual Process *getProcessPtr() = 0; 163#endif 164 165 virtual Status status() const = 0; 166 167 virtual void setStatus(Status new_status) = 0; 168 169 /// Set the status to Active. Optional delay indicates number of 170 /// cycles to wait before beginning execution. 171 virtual void activate(int delay = 1) = 0; 172 173 /// Set the status to Suspended. 174 virtual void suspend(int delay = 0) = 0; 175 176 /// Set the status to Halted. 177 virtual void halt(int delay = 0) = 0; 178 179#if FULL_SYSTEM 180 virtual void dumpFuncProfile() = 0; 181#endif 182 183 virtual void takeOverFrom(ThreadContext *old_context) = 0; 184 185 virtual void regStats(const std::string &name) = 0; 186 187 virtual void serialize(std::ostream &os) = 0; 188 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 189 190#if FULL_SYSTEM 191 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 192 193 // Not necessarily the best location for these... 194 // Having an extra function just to read these is obnoxious 195 virtual Tick readLastActivate() = 0; 196 virtual Tick readLastSuspend() = 0; 197 198 virtual void profileClear() = 0; 199 virtual void profileSample() = 0; 200#endif 201 202 virtual void copyArchRegs(ThreadContext *tc) = 0; 203 204 virtual void clearArchRegs() = 0; 205 206 // 207 // New accessors for new decoder. 208 // 209 virtual uint64_t readIntReg(int reg_idx) = 0; 210 211 virtual FloatReg readFloatReg(int reg_idx) = 0; 212 213 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 214 215 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 216 217 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 218 219 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 220 221 virtual TheISA::PCState pcState() = 0; 222 223 virtual void pcState(const TheISA::PCState &val) = 0; 224 225#if USE_CHECKER 226 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 227#endif 228 229 virtual Addr instAddr() = 0; 230 231 virtual Addr nextInstAddr() = 0; 232 233 virtual MicroPC microPC() = 0; 234 235 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 236 237 virtual MiscReg readMiscReg(int misc_reg) = 0; 238 239 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 240 241 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 242 243 virtual int flattenIntIndex(int reg) = 0; 244 virtual int flattenFloatIndex(int reg) = 0; 245 246 virtual uint64_t 247 readRegOtherThread(int misc_reg, ThreadID tid) 248 { 249 return 0; 250 } 251 252 virtual void 253 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 254 { 255 } 256 257 // Also not necessarily the best location for these two. Hopefully will go 258 // away once we decide upon where st cond failures goes. 259 virtual unsigned readStCondFailures() = 0; 260 261 virtual void setStCondFailures(unsigned sc_failures) = 0; 262 263 // Only really makes sense for old CPU model. Still could be useful though. 264 virtual bool misspeculating() = 0; 265 266#if !FULL_SYSTEM 267 // Same with st cond failures. 268 virtual Counter readFuncExeInst() = 0; 269 270 virtual void syscall(int64_t callnum) = 0; 271 272 // This function exits the thread context in the CPU and returns 273 // 1 if the CPU has no more active threads (meaning it's OK to exit); 274 // Used in syscall-emulation mode when a thread calls the exit syscall. 275 virtual int exit() { return 1; }; 276#endif 277 278 /** function to compare two thread contexts (for debugging) */ 279 static void compare(ThreadContext *one, ThreadContext *two); 280}; 281 282/** 283 * ProxyThreadContext class that provides a way to implement a 284 * ThreadContext without having to derive from it. ThreadContext is an 285 * abstract class, so anything that derives from it and uses its 286 * interface will pay the overhead of virtual function calls. This 287 * class is created to enable a user-defined Thread object to be used 288 * wherever ThreadContexts are used, without paying the overhead of 289 * virtual function calls when it is used by itself. See 290 * simple_thread.hh for an example of this. 291 */ 292template <class TC> 293class ProxyThreadContext : public ThreadContext 294{ 295 public: 296 ProxyThreadContext(TC *actual_tc) 297 { actualTC = actual_tc; } 298 299 private: 300 TC *actualTC; 301 302 public: 303 304 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 305 306 int cpuId() { return actualTC->cpuId(); } 307 308 int threadId() { return actualTC->threadId(); } 309 310 void setThreadId(int id) { return actualTC->setThreadId(id); } 311 312 int contextId() { return actualTC->contextId(); } 313 314 void setContextId(int id) { actualTC->setContextId(id); } 315 316 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 317 318 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 319 320#if USE_CHECKER 321 BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 322#endif 323 324 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 325 326 System *getSystemPtr() { return actualTC->getSystemPtr(); } 327 328#if FULL_SYSTEM 329 TheISA::Kernel::Statistics *getKernelStats() 330 { return actualTC->getKernelStats(); } 331 332 PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 333 334 FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } 335 336 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 337#else 338 SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } 339 340 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 341#endif 342 343 Status status() const { return actualTC->status(); } 344 345 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 346 347 /// Set the status to Active. Optional delay indicates number of 348 /// cycles to wait before beginning execution. 349 void activate(int delay = 1) { actualTC->activate(delay); } 350 351 /// Set the status to Suspended. 352 void suspend(int delay = 0) { actualTC->suspend(); } 353 354 /// Set the status to Halted. 355 void halt(int delay = 0) { actualTC->halt(); } 356 357#if FULL_SYSTEM 358 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 359#endif 360 361 void takeOverFrom(ThreadContext *oldContext) 362 { actualTC->takeOverFrom(oldContext); } 363 364 void regStats(const std::string &name) { actualTC->regStats(name); } 365 366 void serialize(std::ostream &os) { actualTC->serialize(os); } 367 void unserialize(Checkpoint *cp, const std::string §ion) 368 { actualTC->unserialize(cp, section); } 369 370#if FULL_SYSTEM 371 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 372 373 Tick readLastActivate() { return actualTC->readLastActivate(); } 374 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 375 376 void profileClear() { return actualTC->profileClear(); } 377 void profileSample() { return actualTC->profileSample(); } 378#endif 379 380 // @todo: Do I need this? 381 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 382 383 void clearArchRegs() { actualTC->clearArchRegs(); } 384 385 // 386 // New accessors for new decoder. 387 // 388 uint64_t readIntReg(int reg_idx) 389 { return actualTC->readIntReg(reg_idx); } 390 391 FloatReg readFloatReg(int reg_idx) 392 { return actualTC->readFloatReg(reg_idx); } 393 394 FloatRegBits readFloatRegBits(int reg_idx) 395 { return actualTC->readFloatRegBits(reg_idx); } 396 397 void setIntReg(int reg_idx, uint64_t val) 398 { actualTC->setIntReg(reg_idx, val); } 399 400 void setFloatReg(int reg_idx, FloatReg val) 401 { actualTC->setFloatReg(reg_idx, val); } 402 403 void setFloatRegBits(int reg_idx, FloatRegBits val) 404 { actualTC->setFloatRegBits(reg_idx, val); } 405 406 TheISA::PCState pcState() { return actualTC->pcState(); } 407 408 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 409 410#if USE_CHECKER 411 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 412#endif 413 414 Addr instAddr() { return actualTC->instAddr(); } 415 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 416 MicroPC microPC() { return actualTC->microPC(); } 417 418 bool readPredicate() { return actualTC->readPredicate(); } 419 420 void setPredicate(bool val) 421 { actualTC->setPredicate(val); } 422 423 MiscReg readMiscRegNoEffect(int misc_reg) 424 { return actualTC->readMiscRegNoEffect(misc_reg); } 425 426 MiscReg readMiscReg(int misc_reg) 427 { return actualTC->readMiscReg(misc_reg); } 428 429 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 430 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 431 432 void setMiscReg(int misc_reg, const MiscReg &val) 433 { return actualTC->setMiscReg(misc_reg, val); } 434 435 int flattenIntIndex(int reg) 436 { return actualTC->flattenIntIndex(reg); } 437 438 int flattenFloatIndex(int reg) 439 { return actualTC->flattenFloatIndex(reg); } 440 441 unsigned readStCondFailures() 442 { return actualTC->readStCondFailures(); } 443 444 void setStCondFailures(unsigned sc_failures) 445 { actualTC->setStCondFailures(sc_failures); } 446 447 // @todo: Fix this! 448 bool misspeculating() { return actualTC->misspeculating(); } 449 450#if !FULL_SYSTEM 451 void syscall(int64_t callnum) 452 { actualTC->syscall(callnum); } 453 454 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 455#endif 456}; 457 458#endif 459