thread_context.hh revision 7720:65d338a8dba4
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_THREAD_CONTEXT_HH__
32#define __CPU_THREAD_CONTEXT_HH__
33
34#include <string>
35#include <iostream>
36
37#include "arch/registers.hh"
38#include "arch/types.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "config/the_isa.hh"
42
43// @todo: Figure out a more architecture independent way to obtain the ITB and
44// DTB pointers.
45namespace TheISA
46{
47    class TLB;
48}
49class BaseCPU;
50class Checkpoint;
51class EndQuiesceEvent;
52class TranslatingPort;
53class FunctionalPort;
54class VirtualPort;
55class Process;
56class System;
57namespace TheISA {
58    namespace Kernel {
59        class Statistics;
60    };
61};
62
63/**
64 * ThreadContext is the external interface to all thread state for
65 * anything outside of the CPU. It provides all accessor methods to
66 * state that might be needed by external objects, ranging from
67 * register values to things such as kernel stats. It is an abstract
68 * base class; the CPU can create its own ThreadContext by either
69 * deriving from it, or using the templated ProxyThreadContext.
70 *
71 * The ThreadContext is slightly different than the ExecContext.  The
72 * ThreadContext provides access to an individual thread's state; an
73 * ExecContext provides ISA access to the CPU (meaning it is
74 * implicitly multithreaded on SMT systems).  Additionally the
75 * ThreadState is an abstract class that exactly defines the
76 * interface; the ExecContext is a more implicit interface that must
77 * be implemented so that the ISA can access whatever state it needs.
78 */
79class ThreadContext
80{
81  protected:
82    typedef TheISA::MachInst MachInst;
83    typedef TheISA::IntReg IntReg;
84    typedef TheISA::FloatReg FloatReg;
85    typedef TheISA::FloatRegBits FloatRegBits;
86    typedef TheISA::MiscReg MiscReg;
87  public:
88
89    enum Status
90    {
91        /// Running.  Instructions should be executed only when
92        /// the context is in this state.
93        Active,
94
95        /// Temporarily inactive.  Entered while waiting for
96        /// synchronization, etc.
97        Suspended,
98
99        /// Permanently shut down.  Entered when target executes
100        /// m5exit pseudo-instruction.  When all contexts enter
101        /// this state, the simulation will terminate.
102        Halted
103    };
104
105    virtual ~ThreadContext() { };
106
107    virtual BaseCPU *getCpuPtr() = 0;
108
109    virtual int cpuId() = 0;
110
111    virtual int threadId() = 0;
112
113    virtual void setThreadId(int id) = 0;
114
115    virtual int contextId() = 0;
116
117    virtual void setContextId(int id) = 0;
118
119    virtual TheISA::TLB *getITBPtr() = 0;
120
121    virtual TheISA::TLB *getDTBPtr() = 0;
122
123    virtual System *getSystemPtr() = 0;
124
125#if FULL_SYSTEM
126    virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
127
128    virtual FunctionalPort *getPhysPort() = 0;
129
130    virtual VirtualPort *getVirtPort() = 0;
131
132    virtual void connectMemPorts(ThreadContext *tc) = 0;
133#else
134    virtual TranslatingPort *getMemPort() = 0;
135
136    virtual Process *getProcessPtr() = 0;
137#endif
138
139    virtual Status status() const = 0;
140
141    virtual void setStatus(Status new_status) = 0;
142
143    /// Set the status to Active.  Optional delay indicates number of
144    /// cycles to wait before beginning execution.
145    virtual void activate(int delay = 1) = 0;
146
147    /// Set the status to Suspended.
148    virtual void suspend(int delay = 0) = 0;
149
150    /// Set the status to Halted.
151    virtual void halt(int delay = 0) = 0;
152
153#if FULL_SYSTEM
154    virtual void dumpFuncProfile() = 0;
155#endif
156
157    virtual void takeOverFrom(ThreadContext *old_context) = 0;
158
159    virtual void regStats(const std::string &name) = 0;
160
161    virtual void serialize(std::ostream &os) = 0;
162    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
163
164#if FULL_SYSTEM
165    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
166
167    // Not necessarily the best location for these...
168    // Having an extra function just to read these is obnoxious
169    virtual Tick readLastActivate() = 0;
170    virtual Tick readLastSuspend() = 0;
171
172    virtual void profileClear() = 0;
173    virtual void profileSample() = 0;
174#endif
175
176    virtual void copyArchRegs(ThreadContext *tc) = 0;
177
178    virtual void clearArchRegs() = 0;
179
180    //
181    // New accessors for new decoder.
182    //
183    virtual uint64_t readIntReg(int reg_idx) = 0;
184
185    virtual FloatReg readFloatReg(int reg_idx) = 0;
186
187    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
188
189    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
190
191    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
192
193    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
194
195    virtual TheISA::PCState pcState() = 0;
196
197    virtual void pcState(const TheISA::PCState &val) = 0;
198
199    virtual Addr instAddr() = 0;
200
201    virtual Addr nextInstAddr() = 0;
202
203    virtual MicroPC microPC() = 0;
204
205    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
206
207    virtual MiscReg readMiscReg(int misc_reg) = 0;
208
209    virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
210
211    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
212
213    virtual int flattenIntIndex(int reg) = 0;
214    virtual int flattenFloatIndex(int reg) = 0;
215
216    virtual uint64_t
217    readRegOtherThread(int misc_reg, ThreadID tid)
218    {
219        return 0;
220    }
221
222    virtual void
223    setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
224    {
225    }
226
227    // Also not necessarily the best location for these two.  Hopefully will go
228    // away once we decide upon where st cond failures goes.
229    virtual unsigned readStCondFailures() = 0;
230
231    virtual void setStCondFailures(unsigned sc_failures) = 0;
232
233    // Only really makes sense for old CPU model.  Still could be useful though.
234    virtual bool misspeculating() = 0;
235
236#if !FULL_SYSTEM
237    // Same with st cond failures.
238    virtual Counter readFuncExeInst() = 0;
239
240    virtual void syscall(int64_t callnum) = 0;
241
242    // This function exits the thread context in the CPU and returns
243    // 1 if the CPU has no more active threads (meaning it's OK to exit);
244    // Used in syscall-emulation mode when a  thread calls the exit syscall.
245    virtual int exit() { return 1; };
246#endif
247
248    /** function to compare two thread contexts (for debugging) */
249    static void compare(ThreadContext *one, ThreadContext *two);
250};
251
252/**
253 * ProxyThreadContext class that provides a way to implement a
254 * ThreadContext without having to derive from it. ThreadContext is an
255 * abstract class, so anything that derives from it and uses its
256 * interface will pay the overhead of virtual function calls.  This
257 * class is created to enable a user-defined Thread object to be used
258 * wherever ThreadContexts are used, without paying the overhead of
259 * virtual function calls when it is used by itself.  See
260 * simple_thread.hh for an example of this.
261 */
262template <class TC>
263class ProxyThreadContext : public ThreadContext
264{
265  public:
266    ProxyThreadContext(TC *actual_tc)
267    { actualTC = actual_tc; }
268
269  private:
270    TC *actualTC;
271
272  public:
273
274    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
275
276    int cpuId() { return actualTC->cpuId(); }
277
278    int threadId() { return actualTC->threadId(); }
279
280    void setThreadId(int id) { return actualTC->setThreadId(id); }
281
282    int contextId() { return actualTC->contextId(); }
283
284    void setContextId(int id) { actualTC->setContextId(id); }
285
286    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
287
288    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
289
290    System *getSystemPtr() { return actualTC->getSystemPtr(); }
291
292#if FULL_SYSTEM
293    TheISA::Kernel::Statistics *getKernelStats()
294    { return actualTC->getKernelStats(); }
295
296    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
297
298    VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
299
300    void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
301#else
302    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
303
304    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
305#endif
306
307    Status status() const { return actualTC->status(); }
308
309    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
310
311    /// Set the status to Active.  Optional delay indicates number of
312    /// cycles to wait before beginning execution.
313    void activate(int delay = 1) { actualTC->activate(delay); }
314
315    /// Set the status to Suspended.
316    void suspend(int delay = 0) { actualTC->suspend(); }
317
318    /// Set the status to Halted.
319    void halt(int delay = 0) { actualTC->halt(); }
320
321#if FULL_SYSTEM
322    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
323#endif
324
325    void takeOverFrom(ThreadContext *oldContext)
326    { actualTC->takeOverFrom(oldContext); }
327
328    void regStats(const std::string &name) { actualTC->regStats(name); }
329
330    void serialize(std::ostream &os) { actualTC->serialize(os); }
331    void unserialize(Checkpoint *cp, const std::string &section)
332    { actualTC->unserialize(cp, section); }
333
334#if FULL_SYSTEM
335    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
336
337    Tick readLastActivate() { return actualTC->readLastActivate(); }
338    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
339
340    void profileClear() { return actualTC->profileClear(); }
341    void profileSample() { return actualTC->profileSample(); }
342#endif
343
344    // @todo: Do I need this?
345    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
346
347    void clearArchRegs() { actualTC->clearArchRegs(); }
348
349    //
350    // New accessors for new decoder.
351    //
352    uint64_t readIntReg(int reg_idx)
353    { return actualTC->readIntReg(reg_idx); }
354
355    FloatReg readFloatReg(int reg_idx)
356    { return actualTC->readFloatReg(reg_idx); }
357
358    FloatRegBits readFloatRegBits(int reg_idx)
359    { return actualTC->readFloatRegBits(reg_idx); }
360
361    void setIntReg(int reg_idx, uint64_t val)
362    { actualTC->setIntReg(reg_idx, val); }
363
364    void setFloatReg(int reg_idx, FloatReg val)
365    { actualTC->setFloatReg(reg_idx, val); }
366
367    void setFloatRegBits(int reg_idx, FloatRegBits val)
368    { actualTC->setFloatRegBits(reg_idx, val); }
369
370    TheISA::PCState pcState() { return actualTC->pcState(); }
371
372    void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
373
374    Addr instAddr() { return actualTC->instAddr(); }
375    Addr nextInstAddr() { return actualTC->nextInstAddr(); }
376    MicroPC microPC() { return actualTC->microPC(); }
377
378    bool readPredicate() { return actualTC->readPredicate(); }
379
380    void setPredicate(bool val)
381    { actualTC->setPredicate(val); }
382
383    MiscReg readMiscRegNoEffect(int misc_reg)
384    { return actualTC->readMiscRegNoEffect(misc_reg); }
385
386    MiscReg readMiscReg(int misc_reg)
387    { return actualTC->readMiscReg(misc_reg); }
388
389    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
390    { return actualTC->setMiscRegNoEffect(misc_reg, val); }
391
392    void setMiscReg(int misc_reg, const MiscReg &val)
393    { return actualTC->setMiscReg(misc_reg, val); }
394
395    int flattenIntIndex(int reg)
396    { return actualTC->flattenIntIndex(reg); }
397
398    int flattenFloatIndex(int reg)
399    { return actualTC->flattenFloatIndex(reg); }
400
401    unsigned readStCondFailures()
402    { return actualTC->readStCondFailures(); }
403
404    void setStCondFailures(unsigned sc_failures)
405    { actualTC->setStCondFailures(sc_failures); }
406
407    // @todo: Fix this!
408    bool misspeculating() { return actualTC->misspeculating(); }
409
410#if !FULL_SYSTEM
411    void syscall(int64_t callnum)
412    { actualTC->syscall(callnum); }
413
414    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
415#endif
416};
417
418#endif
419