thread_context.hh revision 7680:f4eda002333b
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include <string> 35#include <iostream> 36 37#include "arch/registers.hh" 38#include "arch/types.hh" 39#include "base/types.hh" 40#include "config/full_system.hh" 41#include "config/the_isa.hh" 42 43// @todo: Figure out a more architecture independent way to obtain the ITB and 44// DTB pointers. 45namespace TheISA 46{ 47 class TLB; 48} 49class BaseCPU; 50class Checkpoint; 51class EndQuiesceEvent; 52class TranslatingPort; 53class FunctionalPort; 54class VirtualPort; 55class Process; 56class System; 57namespace TheISA { 58 namespace Kernel { 59 class Statistics; 60 }; 61}; 62 63/** 64 * ThreadContext is the external interface to all thread state for 65 * anything outside of the CPU. It provides all accessor methods to 66 * state that might be needed by external objects, ranging from 67 * register values to things such as kernel stats. It is an abstract 68 * base class; the CPU can create its own ThreadContext by either 69 * deriving from it, or using the templated ProxyThreadContext. 70 * 71 * The ThreadContext is slightly different than the ExecContext. The 72 * ThreadContext provides access to an individual thread's state; an 73 * ExecContext provides ISA access to the CPU (meaning it is 74 * implicitly multithreaded on SMT systems). Additionally the 75 * ThreadState is an abstract class that exactly defines the 76 * interface; the ExecContext is a more implicit interface that must 77 * be implemented so that the ISA can access whatever state it needs. 78 */ 79class ThreadContext 80{ 81 protected: 82 typedef TheISA::MachInst MachInst; 83 typedef TheISA::IntReg IntReg; 84 typedef TheISA::FloatReg FloatReg; 85 typedef TheISA::FloatRegBits FloatRegBits; 86 typedef TheISA::MiscReg MiscReg; 87 public: 88 89 enum Status 90 { 91 /// Running. Instructions should be executed only when 92 /// the context is in this state. 93 Active, 94 95 /// Temporarily inactive. Entered while waiting for 96 /// synchronization, etc. 97 Suspended, 98 99 /// Permanently shut down. Entered when target executes 100 /// m5exit pseudo-instruction. When all contexts enter 101 /// this state, the simulation will terminate. 102 Halted 103 }; 104 105 virtual ~ThreadContext() { }; 106 107 virtual BaseCPU *getCpuPtr() = 0; 108 109 virtual int cpuId() = 0; 110 111 virtual int threadId() = 0; 112 113 virtual void setThreadId(int id) = 0; 114 115 virtual int contextId() = 0; 116 117 virtual void setContextId(int id) = 0; 118 119 virtual TheISA::TLB *getITBPtr() = 0; 120 121 virtual TheISA::TLB *getDTBPtr() = 0; 122 123 virtual System *getSystemPtr() = 0; 124 125#if FULL_SYSTEM 126 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 127 128 virtual FunctionalPort *getPhysPort() = 0; 129 130 virtual VirtualPort *getVirtPort() = 0; 131 132 virtual void connectMemPorts(ThreadContext *tc) = 0; 133#else 134 virtual TranslatingPort *getMemPort() = 0; 135 136 virtual Process *getProcessPtr() = 0; 137#endif 138 139 virtual Status status() const = 0; 140 141 virtual void setStatus(Status new_status) = 0; 142 143 /// Set the status to Active. Optional delay indicates number of 144 /// cycles to wait before beginning execution. 145 virtual void activate(int delay = 1) = 0; 146 147 /// Set the status to Suspended. 148 virtual void suspend(int delay = 0) = 0; 149 150 /// Set the status to Halted. 151 virtual void halt(int delay = 0) = 0; 152 153#if FULL_SYSTEM 154 virtual void dumpFuncProfile() = 0; 155#endif 156 157 virtual void takeOverFrom(ThreadContext *old_context) = 0; 158 159 virtual void regStats(const std::string &name) = 0; 160 161 virtual void serialize(std::ostream &os) = 0; 162 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 163 164#if FULL_SYSTEM 165 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 166 167 // Not necessarily the best location for these... 168 // Having an extra function just to read these is obnoxious 169 virtual Tick readLastActivate() = 0; 170 virtual Tick readLastSuspend() = 0; 171 172 virtual void profileClear() = 0; 173 virtual void profileSample() = 0; 174#endif 175 176 virtual void copyArchRegs(ThreadContext *tc) = 0; 177 178 virtual void clearArchRegs() = 0; 179 180 // 181 // New accessors for new decoder. 182 // 183 virtual uint64_t readIntReg(int reg_idx) = 0; 184 185 virtual FloatReg readFloatReg(int reg_idx) = 0; 186 187 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 188 189 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 190 191 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 192 193 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 194 195 virtual uint64_t readPC() = 0; 196 197 virtual void setPC(uint64_t val) = 0; 198 199 virtual uint64_t readNextPC() = 0; 200 201 virtual void setNextPC(uint64_t val) = 0; 202 203 virtual uint64_t readNextNPC() = 0; 204 205 virtual void setNextNPC(uint64_t val) = 0; 206 207 virtual uint64_t readMicroPC() = 0; 208 209 virtual void setMicroPC(uint64_t val) = 0; 210 211 virtual uint64_t readNextMicroPC() = 0; 212 213 virtual void setNextMicroPC(uint64_t val) = 0; 214 215 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 216 217 virtual MiscReg readMiscReg(int misc_reg) = 0; 218 219 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 220 221 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 222 223 virtual int flattenIntIndex(int reg) = 0; 224 virtual int flattenFloatIndex(int reg) = 0; 225 226 virtual uint64_t 227 readRegOtherThread(int misc_reg, ThreadID tid) 228 { 229 return 0; 230 } 231 232 virtual void 233 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 234 { 235 } 236 237 // Also not necessarily the best location for these two. Hopefully will go 238 // away once we decide upon where st cond failures goes. 239 virtual unsigned readStCondFailures() = 0; 240 241 virtual void setStCondFailures(unsigned sc_failures) = 0; 242 243 // Only really makes sense for old CPU model. Still could be useful though. 244 virtual bool misspeculating() = 0; 245 246#if !FULL_SYSTEM 247 // Same with st cond failures. 248 virtual Counter readFuncExeInst() = 0; 249 250 virtual void syscall(int64_t callnum) = 0; 251 252 // This function exits the thread context in the CPU and returns 253 // 1 if the CPU has no more active threads (meaning it's OK to exit); 254 // Used in syscall-emulation mode when a thread calls the exit syscall. 255 virtual int exit() { return 1; }; 256#endif 257 258 /** function to compare two thread contexts (for debugging) */ 259 static void compare(ThreadContext *one, ThreadContext *two); 260}; 261 262/** 263 * ProxyThreadContext class that provides a way to implement a 264 * ThreadContext without having to derive from it. ThreadContext is an 265 * abstract class, so anything that derives from it and uses its 266 * interface will pay the overhead of virtual function calls. This 267 * class is created to enable a user-defined Thread object to be used 268 * wherever ThreadContexts are used, without paying the overhead of 269 * virtual function calls when it is used by itself. See 270 * simple_thread.hh for an example of this. 271 */ 272template <class TC> 273class ProxyThreadContext : public ThreadContext 274{ 275 public: 276 ProxyThreadContext(TC *actual_tc) 277 { actualTC = actual_tc; } 278 279 private: 280 TC *actualTC; 281 282 public: 283 284 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 285 286 int cpuId() { return actualTC->cpuId(); } 287 288 int threadId() { return actualTC->threadId(); } 289 290 void setThreadId(int id) { return actualTC->setThreadId(id); } 291 292 int contextId() { return actualTC->contextId(); } 293 294 void setContextId(int id) { actualTC->setContextId(id); } 295 296 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 297 298 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 299 300 System *getSystemPtr() { return actualTC->getSystemPtr(); } 301 302#if FULL_SYSTEM 303 TheISA::Kernel::Statistics *getKernelStats() 304 { return actualTC->getKernelStats(); } 305 306 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 307 308 VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 309 310 void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 311#else 312 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 313 314 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 315#endif 316 317 Status status() const { return actualTC->status(); } 318 319 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 320 321 /// Set the status to Active. Optional delay indicates number of 322 /// cycles to wait before beginning execution. 323 void activate(int delay = 1) { actualTC->activate(delay); } 324 325 /// Set the status to Suspended. 326 void suspend(int delay = 0) { actualTC->suspend(); } 327 328 /// Set the status to Halted. 329 void halt(int delay = 0) { actualTC->halt(); } 330 331#if FULL_SYSTEM 332 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 333#endif 334 335 void takeOverFrom(ThreadContext *oldContext) 336 { actualTC->takeOverFrom(oldContext); } 337 338 void regStats(const std::string &name) { actualTC->regStats(name); } 339 340 void serialize(std::ostream &os) { actualTC->serialize(os); } 341 void unserialize(Checkpoint *cp, const std::string §ion) 342 { actualTC->unserialize(cp, section); } 343 344#if FULL_SYSTEM 345 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 346 347 Tick readLastActivate() { return actualTC->readLastActivate(); } 348 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 349 350 void profileClear() { return actualTC->profileClear(); } 351 void profileSample() { return actualTC->profileSample(); } 352#endif 353 354 // @todo: Do I need this? 355 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 356 357 void clearArchRegs() { actualTC->clearArchRegs(); } 358 359 // 360 // New accessors for new decoder. 361 // 362 uint64_t readIntReg(int reg_idx) 363 { return actualTC->readIntReg(reg_idx); } 364 365 FloatReg readFloatReg(int reg_idx) 366 { return actualTC->readFloatReg(reg_idx); } 367 368 FloatRegBits readFloatRegBits(int reg_idx) 369 { return actualTC->readFloatRegBits(reg_idx); } 370 371 void setIntReg(int reg_idx, uint64_t val) 372 { actualTC->setIntReg(reg_idx, val); } 373 374 void setFloatReg(int reg_idx, FloatReg val) 375 { actualTC->setFloatReg(reg_idx, val); } 376 377 void setFloatRegBits(int reg_idx, FloatRegBits val) 378 { actualTC->setFloatRegBits(reg_idx, val); } 379 380 uint64_t readPC() { return actualTC->readPC(); } 381 382 void setPC(uint64_t val) { actualTC->setPC(val); } 383 384 uint64_t readNextPC() { return actualTC->readNextPC(); } 385 386 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 387 388 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 389 390 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 391 392 uint64_t readMicroPC() { return actualTC->readMicroPC(); } 393 394 void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 395 396 uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 397 398 void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 399 400 bool readPredicate() { return actualTC->readPredicate(); } 401 402 void setPredicate(bool val) 403 { actualTC->setPredicate(val); } 404 405 MiscReg readMiscRegNoEffect(int misc_reg) 406 { return actualTC->readMiscRegNoEffect(misc_reg); } 407 408 MiscReg readMiscReg(int misc_reg) 409 { return actualTC->readMiscReg(misc_reg); } 410 411 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 412 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 413 414 void setMiscReg(int misc_reg, const MiscReg &val) 415 { return actualTC->setMiscReg(misc_reg, val); } 416 417 int flattenIntIndex(int reg) 418 { return actualTC->flattenIntIndex(reg); } 419 420 int flattenFloatIndex(int reg) 421 { return actualTC->flattenFloatIndex(reg); } 422 423 unsigned readStCondFailures() 424 { return actualTC->readStCondFailures(); } 425 426 void setStCondFailures(unsigned sc_failures) 427 { actualTC->setStCondFailures(sc_failures); } 428 429 // @todo: Fix this! 430 bool misspeculating() { return actualTC->misspeculating(); } 431 432#if !FULL_SYSTEM 433 void syscall(int64_t callnum) 434 { actualTC->syscall(callnum); } 435 436 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 437#endif 438}; 439 440#endif 441