thread_context.hh revision 5222:bb733a878f85
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "arch/regfile.hh" 35#include "arch/types.hh" 36#include "config/full_system.hh" 37#include "mem/request.hh" 38#include "sim/faults.hh" 39#include "sim/host.hh" 40#include "sim/serialize.hh" 41#include "sim/syscallreturn.hh" 42#include "sim/byteswap.hh" 43 44// @todo: Figure out a more architecture independent way to obtain the ITB and 45// DTB pointers. 46namespace TheISA 47{ 48 class DTB; 49 class ITB; 50} 51class BaseCPU; 52class EndQuiesceEvent; 53class Event; 54class TranslatingPort; 55class FunctionalPort; 56class VirtualPort; 57class Process; 58class System; 59namespace TheISA { 60 namespace Kernel { 61 class Statistics; 62 }; 63}; 64 65/** 66 * ThreadContext is the external interface to all thread state for 67 * anything outside of the CPU. It provides all accessor methods to 68 * state that might be needed by external objects, ranging from 69 * register values to things such as kernel stats. It is an abstract 70 * base class; the CPU can create its own ThreadContext by either 71 * deriving from it, or using the templated ProxyThreadContext. 72 * 73 * The ThreadContext is slightly different than the ExecContext. The 74 * ThreadContext provides access to an individual thread's state; an 75 * ExecContext provides ISA access to the CPU (meaning it is 76 * implicitly multithreaded on SMT systems). Additionally the 77 * ThreadState is an abstract class that exactly defines the 78 * interface; the ExecContext is a more implicit interface that must 79 * be implemented so that the ISA can access whatever state it needs. 80 */ 81class ThreadContext 82{ 83 protected: 84 typedef TheISA::RegFile RegFile; 85 typedef TheISA::MachInst MachInst; 86 typedef TheISA::IntReg IntReg; 87 typedef TheISA::FloatReg FloatReg; 88 typedef TheISA::FloatRegBits FloatRegBits; 89 typedef TheISA::MiscRegFile MiscRegFile; 90 typedef TheISA::MiscReg MiscReg; 91 public: 92 enum Status 93 { 94 /// Initialized but not running yet. All CPUs start in 95 /// this state, but most transition to Active on cycle 1. 96 /// In MP or SMT systems, non-primary contexts will stay 97 /// in this state until a thread is assigned to them. 98 Unallocated, 99 100 /// Running. Instructions should be executed only when 101 /// the context is in this state. 102 Active, 103 104 /// Temporarily inactive. Entered while waiting for 105 /// synchronization, etc. 106 Suspended, 107 108 /// Permanently shut down. Entered when target executes 109 /// m5exit pseudo-instruction. When all contexts enter 110 /// this state, the simulation will terminate. 111 Halted 112 }; 113 114 virtual ~ThreadContext() { }; 115 116 virtual BaseCPU *getCpuPtr() = 0; 117 118 virtual void setCpuId(int id) = 0; 119 120 virtual int readCpuId() = 0; 121 122 virtual TheISA::ITB *getITBPtr() = 0; 123 124 virtual TheISA::DTB *getDTBPtr() = 0; 125 126#if FULL_SYSTEM 127 virtual System *getSystemPtr() = 0; 128 129 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 130 131 virtual FunctionalPort *getPhysPort() = 0; 132 133 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 134 135 virtual void delVirtPort(VirtualPort *vp) = 0; 136 137 virtual void connectMemPorts() = 0; 138#else 139 virtual TranslatingPort *getMemPort() = 0; 140 141 virtual Process *getProcessPtr() = 0; 142#endif 143 144 virtual Status status() const = 0; 145 146 virtual void setStatus(Status new_status) = 0; 147 148 /// Set the status to Active. Optional delay indicates number of 149 /// cycles to wait before beginning execution. 150 virtual void activate(int delay = 1) = 0; 151 152 /// Set the status to Suspended. 153 virtual void suspend() = 0; 154 155 /// Set the status to Unallocated. 156 virtual void deallocate(int delay = 0) = 0; 157 158 /// Set the status to Halted. 159 virtual void halt() = 0; 160 161#if FULL_SYSTEM 162 virtual void dumpFuncProfile() = 0; 163#endif 164 165 virtual void takeOverFrom(ThreadContext *old_context) = 0; 166 167 virtual void regStats(const std::string &name) = 0; 168 169 virtual void serialize(std::ostream &os) = 0; 170 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 171 172#if FULL_SYSTEM 173 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 174 175 // Not necessarily the best location for these... 176 // Having an extra function just to read these is obnoxious 177 virtual Tick readLastActivate() = 0; 178 virtual Tick readLastSuspend() = 0; 179 180 virtual void profileClear() = 0; 181 virtual void profileSample() = 0; 182#endif 183 184 virtual int getThreadNum() = 0; 185 186 // Also somewhat obnoxious. Really only used for the TLB fault. 187 // However, may be quite useful in SPARC. 188 virtual TheISA::MachInst getInst() = 0; 189 190 virtual void copyArchRegs(ThreadContext *tc) = 0; 191 192 virtual void clearArchRegs() = 0; 193 194 // 195 // New accessors for new decoder. 196 // 197 virtual uint64_t readIntReg(int reg_idx) = 0; 198 199 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 200 201 virtual FloatReg readFloatReg(int reg_idx) = 0; 202 203 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 204 205 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 206 207 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 208 209 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 210 211 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 212 213 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 214 215 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 216 217 virtual uint64_t readPC() = 0; 218 219 virtual void setPC(uint64_t val) = 0; 220 221 virtual uint64_t readNextPC() = 0; 222 223 virtual void setNextPC(uint64_t val) = 0; 224 225 virtual uint64_t readNextNPC() = 0; 226 227 virtual void setNextNPC(uint64_t val) = 0; 228 229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 230 231 virtual MiscReg readMiscReg(int misc_reg) = 0; 232 233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 234 235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 236 237 virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } 238 239 virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; 240 241 virtual void setShadowSet(int css) = 0; 242 243 // Also not necessarily the best location for these two. Hopefully will go 244 // away once we decide upon where st cond failures goes. 245 virtual unsigned readStCondFailures() = 0; 246 247 virtual void setStCondFailures(unsigned sc_failures) = 0; 248 249 // Only really makes sense for old CPU model. Still could be useful though. 250 virtual bool misspeculating() = 0; 251 252#if !FULL_SYSTEM 253 virtual IntReg getSyscallArg(int i) = 0; 254 255 // used to shift args for indirect syscall 256 virtual void setSyscallArg(int i, IntReg val) = 0; 257 258 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 259 260 // Same with st cond failures. 261 virtual Counter readFuncExeInst() = 0; 262 263 virtual void syscall(int64_t callnum) = 0; 264 265 // This function exits the thread context in the CPU and returns 266 // 1 if the CPU has no more active threads (meaning it's OK to exit); 267 // Used in syscall-emulation mode when a thread calls the exit syscall. 268 virtual int exit() { return 1; }; 269#endif 270 271 virtual void changeRegFileContext(TheISA::RegContextParam param, 272 TheISA::RegContextVal val) = 0; 273 274 /** function to compare two thread contexts (for debugging) */ 275 static void compare(ThreadContext *one, ThreadContext *two); 276}; 277 278/** 279 * ProxyThreadContext class that provides a way to implement a 280 * ThreadContext without having to derive from it. ThreadContext is an 281 * abstract class, so anything that derives from it and uses its 282 * interface will pay the overhead of virtual function calls. This 283 * class is created to enable a user-defined Thread object to be used 284 * wherever ThreadContexts are used, without paying the overhead of 285 * virtual function calls when it is used by itself. See 286 * simple_thread.hh for an example of this. 287 */ 288template <class TC> 289class ProxyThreadContext : public ThreadContext 290{ 291 public: 292 ProxyThreadContext(TC *actual_tc) 293 { actualTC = actual_tc; } 294 295 private: 296 TC *actualTC; 297 298 public: 299 300 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 301 302 void setCpuId(int id) { actualTC->setCpuId(id); } 303 304 int readCpuId() { return actualTC->readCpuId(); } 305 306 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 307 308 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 309 310#if FULL_SYSTEM 311 System *getSystemPtr() { return actualTC->getSystemPtr(); } 312 313 TheISA::Kernel::Statistics *getKernelStats() 314 { return actualTC->getKernelStats(); } 315 316 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 317 318 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 319 320 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 321 322 void connectMemPorts() { actualTC->connectMemPorts(); } 323#else 324 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 325 326 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 327#endif 328 329 Status status() const { return actualTC->status(); } 330 331 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 332 333 /// Set the status to Active. Optional delay indicates number of 334 /// cycles to wait before beginning execution. 335 void activate(int delay = 1) { actualTC->activate(delay); } 336 337 /// Set the status to Suspended. 338 void suspend() { actualTC->suspend(); } 339 340 /// Set the status to Unallocated. 341 void deallocate(int delay = 0) { actualTC->deallocate(); } 342 343 /// Set the status to Halted. 344 void halt() { actualTC->halt(); } 345 346#if FULL_SYSTEM 347 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 348#endif 349 350 void takeOverFrom(ThreadContext *oldContext) 351 { actualTC->takeOverFrom(oldContext); } 352 353 void regStats(const std::string &name) { actualTC->regStats(name); } 354 355 void serialize(std::ostream &os) { actualTC->serialize(os); } 356 void unserialize(Checkpoint *cp, const std::string §ion) 357 { actualTC->unserialize(cp, section); } 358 359#if FULL_SYSTEM 360 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 361 362 Tick readLastActivate() { return actualTC->readLastActivate(); } 363 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 364 365 void profileClear() { return actualTC->profileClear(); } 366 void profileSample() { return actualTC->profileSample(); } 367#endif 368 369 int getThreadNum() { return actualTC->getThreadNum(); } 370 371 // @todo: Do I need this? 372 MachInst getInst() { return actualTC->getInst(); } 373 374 // @todo: Do I need this? 375 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 376 377 void clearArchRegs() { actualTC->clearArchRegs(); } 378 379 // 380 // New accessors for new decoder. 381 // 382 uint64_t readIntReg(int reg_idx) 383 { return actualTC->readIntReg(reg_idx); } 384 385 FloatReg readFloatReg(int reg_idx, int width) 386 { return actualTC->readFloatReg(reg_idx, width); } 387 388 FloatReg readFloatReg(int reg_idx) 389 { return actualTC->readFloatReg(reg_idx); } 390 391 FloatRegBits readFloatRegBits(int reg_idx, int width) 392 { return actualTC->readFloatRegBits(reg_idx, width); } 393 394 FloatRegBits readFloatRegBits(int reg_idx) 395 { return actualTC->readFloatRegBits(reg_idx); } 396 397 void setIntReg(int reg_idx, uint64_t val) 398 { actualTC->setIntReg(reg_idx, val); } 399 400 void setFloatReg(int reg_idx, FloatReg val, int width) 401 { actualTC->setFloatReg(reg_idx, val, width); } 402 403 void setFloatReg(int reg_idx, FloatReg val) 404 { actualTC->setFloatReg(reg_idx, val); } 405 406 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 407 { actualTC->setFloatRegBits(reg_idx, val, width); } 408 409 void setFloatRegBits(int reg_idx, FloatRegBits val) 410 { actualTC->setFloatRegBits(reg_idx, val); } 411 412 void setShadowSet(int css){ 413 return actualTC->setShadowSet(css); 414 } 415 416 uint64_t readPC() { return actualTC->readPC(); } 417 418 void setPC(uint64_t val) { actualTC->setPC(val); } 419 420 uint64_t readNextPC() { return actualTC->readNextPC(); } 421 422 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 423 424 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 425 426 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 427 428 MiscReg readMiscRegNoEffect(int misc_reg) 429 { return actualTC->readMiscRegNoEffect(misc_reg); } 430 431 MiscReg readMiscReg(int misc_reg) 432 { return actualTC->readMiscReg(misc_reg); } 433 434 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 435 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 436 437 void setMiscReg(int misc_reg, const MiscReg &val) 438 { return actualTC->setMiscReg(misc_reg, val); } 439 440 unsigned readStCondFailures() 441 { return actualTC->readStCondFailures(); } 442 443 void setStCondFailures(unsigned sc_failures) 444 { actualTC->setStCondFailures(sc_failures); } 445 446 // @todo: Fix this! 447 bool misspeculating() { return actualTC->misspeculating(); } 448 449#if !FULL_SYSTEM 450 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 451 452 // used to shift args for indirect syscall 453 void setSyscallArg(int i, IntReg val) 454 { actualTC->setSyscallArg(i, val); } 455 456 void setSyscallReturn(SyscallReturn return_value) 457 { actualTC->setSyscallReturn(return_value); } 458 459 void syscall(int64_t callnum) 460 { actualTC->syscall(callnum); } 461 462 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 463#endif 464 465 void changeRegFileContext(TheISA::RegContextParam param, 466 TheISA::RegContextVal val) 467 { 468 actualTC->changeRegFileContext(param, val); 469 } 470}; 471 472#endif 473