thread_context.hh revision 2719:d73e952240aa
14202Sbinkertn@umich.edu/* 24202Sbinkertn@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34202Sbinkertn@umich.edu * All rights reserved. 44202Sbinkertn@umich.edu * 54202Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64202Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74202Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94202Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114202Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124202Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134202Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144202Sbinkertn@umich.edu * this software without specific prior written permission. 154202Sbinkertn@umich.edu * 164202Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174202Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184202Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194202Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204202Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224202Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244202Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254202Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264202Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274202Sbinkertn@umich.edu * 284202Sbinkertn@umich.edu * Authors: Kevin Lim 294202Sbinkertn@umich.edu */ 304202Sbinkertn@umich.edu 314202Sbinkertn@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 324202Sbinkertn@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 334486Sbinkertn@umich.edu 344486Sbinkertn@umich.edu#include "config/full_system.hh" 356165Ssanchezd@stanford.edu#include "mem/request.hh" 366168Snate@binkert.org#include "sim/faults.hh" 374202Sbinkertn@umich.edu#include "sim/host.hh" 384202Sbinkertn@umich.edu#include "sim/serialize.hh" 394202Sbinkertn@umich.edu#include "sim/byteswap.hh" 408761Sgblack@eecs.umich.edu 414202Sbinkertn@umich.edu// @todo: Figure out a more architecture independent way to obtain the ITB and 424202Sbinkertn@umich.edu// DTB pointers. 434202Sbinkertn@umich.educlass AlphaDTB; 448761Sgblack@eecs.umich.educlass AlphaITB; 456168Snate@binkert.orgclass BaseCPU; 467768SAli.Saidi@ARM.comclass EndQuiesceEvent; 477768SAli.Saidi@ARM.comclass Event; 487768SAli.Saidi@ARM.comclass TranslatingPort; 497768SAli.Saidi@ARM.comclass FunctionalPort; 508762Sgblack@eecs.umich.educlass VirtualPort; 517768SAli.Saidi@ARM.comclass Process; 528761Sgblack@eecs.umich.educlass System; 534202Sbinkertn@umich.edunamespace Kernel { 545192Ssaidi@eecs.umich.edu class Statistics; 558335Snate@binkert.org}; 568335Snate@binkert.org 578335Snate@binkert.org/** 588335Snate@binkert.org * ThreadContext is the external interface to all thread state for 598335Snate@binkert.org * anything outside of the CPU. It provides all accessor methods to 608335Snate@binkert.org * state that might be needed by external objects, ranging from 617780Snilay@cs.wisc.edu * register values to things such as kernel stats. It is an abstract 628335Snate@binkert.org * base class; the CPU can create its own ThreadContext by either 638335Snate@binkert.org * deriving from it, or using the templated ProxyThreadContext. 648335Snate@binkert.org * 658335Snate@binkert.org * The ThreadContext is slightly different than the ExecContext. The 668335Snate@binkert.org * ThreadContext provides access to an individual thread's state; an 678335Snate@binkert.org * ExecContext provides ISA access to the CPU (meaning it is 688335Snate@binkert.org * implicitly multithreaded on SMT systems). Additionally the 698335Snate@binkert.org * ThreadState is an abstract class that exactly defines the 708335Snate@binkert.org * interface; the ExecContext is a more implicit interface that must 718335Snate@binkert.org * be implemented so that the ISA can access whatever state it needs. 728335Snate@binkert.org */ 737780Snilay@cs.wisc.educlass ThreadContext 747780Snilay@cs.wisc.edu{ 757780Snilay@cs.wisc.edu protected: 768161SBrad.Beckmann@amd.com typedef TheISA::RegFile RegFile; 77 typedef TheISA::MachInst MachInst; 78 typedef TheISA::IntReg IntReg; 79 typedef TheISA::FloatReg FloatReg; 80 typedef TheISA::FloatRegBits FloatRegBits; 81 typedef TheISA::MiscRegFile MiscRegFile; 82 typedef TheISA::MiscReg MiscReg; 83 public: 84 enum Status 85 { 86 /// Initialized but not running yet. All CPUs start in 87 /// this state, but most transition to Active on cycle 1. 88 /// In MP or SMT systems, non-primary contexts will stay 89 /// in this state until a thread is assigned to them. 90 Unallocated, 91 92 /// Running. Instructions should be executed only when 93 /// the context is in this state. 94 Active, 95 96 /// Temporarily inactive. Entered while waiting for 97 /// synchronization, etc. 98 Suspended, 99 100 /// Permanently shut down. Entered when target executes 101 /// m5exit pseudo-instruction. When all contexts enter 102 /// this state, the simulation will terminate. 103 Halted 104 }; 105 106 virtual ~ThreadContext() { }; 107 108 virtual BaseCPU *getCpuPtr() = 0; 109 110 virtual void setCpuId(int id) = 0; 111 112 virtual int readCpuId() = 0; 113 114#if FULL_SYSTEM 115 virtual System *getSystemPtr() = 0; 116 117 virtual AlphaITB *getITBPtr() = 0; 118 119 virtual AlphaDTB * getDTBPtr() = 0; 120 121 virtual Kernel::Statistics *getKernelStats() = 0; 122 123 virtual FunctionalPort *getPhysPort() = 0; 124 125 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 126 127 virtual void delVirtPort(VirtualPort *vp) = 0; 128#else 129 virtual TranslatingPort *getMemPort() = 0; 130 131 virtual Process *getProcessPtr() = 0; 132#endif 133 134 virtual Status status() const = 0; 135 136 virtual void setStatus(Status new_status) = 0; 137 138 /// Set the status to Active. Optional delay indicates number of 139 /// cycles to wait before beginning execution. 140 virtual void activate(int delay = 1) = 0; 141 142 /// Set the status to Suspended. 143 virtual void suspend() = 0; 144 145 /// Set the status to Unallocated. 146 virtual void deallocate() = 0; 147 148 /// Set the status to Halted. 149 virtual void halt() = 0; 150 151#if FULL_SYSTEM 152 virtual void dumpFuncProfile() = 0; 153#endif 154 155 virtual void takeOverFrom(ThreadContext *old_context) = 0; 156 157 virtual void regStats(const std::string &name) = 0; 158 159 virtual void serialize(std::ostream &os) = 0; 160 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 161 162#if FULL_SYSTEM 163 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 164 165 // Not necessarily the best location for these... 166 // Having an extra function just to read these is obnoxious 167 virtual Tick readLastActivate() = 0; 168 virtual Tick readLastSuspend() = 0; 169 170 virtual void profileClear() = 0; 171 virtual void profileSample() = 0; 172#endif 173 174 virtual int getThreadNum() = 0; 175 176 // Also somewhat obnoxious. Really only used for the TLB fault. 177 // However, may be quite useful in SPARC. 178 virtual TheISA::MachInst getInst() = 0; 179 180 virtual void copyArchRegs(ThreadContext *tc) = 0; 181 182 virtual void clearArchRegs() = 0; 183 184 // 185 // New accessors for new decoder. 186 // 187 virtual uint64_t readIntReg(int reg_idx) = 0; 188 189 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 190 191 virtual FloatReg readFloatReg(int reg_idx) = 0; 192 193 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 194 195 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 196 197 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 198 199 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 200 201 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 202 203 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 204 205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 206 207 virtual uint64_t readPC() = 0; 208 209 virtual void setPC(uint64_t val) = 0; 210 211 virtual uint64_t readNextPC() = 0; 212 213 virtual void setNextPC(uint64_t val) = 0; 214 215 virtual uint64_t readNextNPC() = 0; 216 217 virtual void setNextNPC(uint64_t val) = 0; 218 219 virtual MiscReg readMiscReg(int misc_reg) = 0; 220 221 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 222 223 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 224 225 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 226 227 // Also not necessarily the best location for these two. Hopefully will go 228 // away once we decide upon where st cond failures goes. 229 virtual unsigned readStCondFailures() = 0; 230 231 virtual void setStCondFailures(unsigned sc_failures) = 0; 232 233#if FULL_SYSTEM 234 virtual bool inPalMode() = 0; 235#endif 236 237 // Only really makes sense for old CPU model. Still could be useful though. 238 virtual bool misspeculating() = 0; 239 240#if !FULL_SYSTEM 241 virtual IntReg getSyscallArg(int i) = 0; 242 243 // used to shift args for indirect syscall 244 virtual void setSyscallArg(int i, IntReg val) = 0; 245 246 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 247 248 // Same with st cond failures. 249 virtual Counter readFuncExeInst() = 0; 250#endif 251 252 virtual void changeRegFileContext(RegFile::ContextParam param, 253 RegFile::ContextVal val) = 0; 254}; 255 256/** 257 * ProxyThreadContext class that provides a way to implement a 258 * ThreadContext without having to derive from it. ThreadContext is an 259 * abstract class, so anything that derives from it and uses its 260 * interface will pay the overhead of virtual function calls. This 261 * class is created to enable a user-defined Thread object to be used 262 * wherever ThreadContexts are used, without paying the overhead of 263 * virtual function calls when it is used by itself. See 264 * simple_thread.hh for an example of this. 265 */ 266template <class TC> 267class ProxyThreadContext : public ThreadContext 268{ 269 public: 270 ProxyThreadContext(TC *actual_tc) 271 { actualTC = actual_tc; } 272 273 private: 274 TC *actualTC; 275 276 public: 277 278 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 279 280 void setCpuId(int id) { actualTC->setCpuId(id); } 281 282 int readCpuId() { return actualTC->readCpuId(); } 283 284#if FULL_SYSTEM 285 System *getSystemPtr() { return actualTC->getSystemPtr(); } 286 287 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } 288 289 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } 290 291 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 292 293 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 294 295 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 296 297 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 298#else 299 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 300 301 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 302#endif 303 304 Status status() const { return actualTC->status(); } 305 306 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 307 308 /// Set the status to Active. Optional delay indicates number of 309 /// cycles to wait before beginning execution. 310 void activate(int delay = 1) { actualTC->activate(delay); } 311 312 /// Set the status to Suspended. 313 void suspend() { actualTC->suspend(); } 314 315 /// Set the status to Unallocated. 316 void deallocate() { actualTC->deallocate(); } 317 318 /// Set the status to Halted. 319 void halt() { actualTC->halt(); } 320 321#if FULL_SYSTEM 322 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 323#endif 324 325 void takeOverFrom(ThreadContext *oldContext) 326 { actualTC->takeOverFrom(oldContext); } 327 328 void regStats(const std::string &name) { actualTC->regStats(name); } 329 330 void serialize(std::ostream &os) { actualTC->serialize(os); } 331 void unserialize(Checkpoint *cp, const std::string §ion) 332 { actualTC->unserialize(cp, section); } 333 334#if FULL_SYSTEM 335 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 336 337 Tick readLastActivate() { return actualTC->readLastActivate(); } 338 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 339 340 void profileClear() { return actualTC->profileClear(); } 341 void profileSample() { return actualTC->profileSample(); } 342#endif 343 344 int getThreadNum() { return actualTC->getThreadNum(); } 345 346 // @todo: Do I need this? 347 MachInst getInst() { return actualTC->getInst(); } 348 349 // @todo: Do I need this? 350 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 351 352 void clearArchRegs() { actualTC->clearArchRegs(); } 353 354 // 355 // New accessors for new decoder. 356 // 357 uint64_t readIntReg(int reg_idx) 358 { return actualTC->readIntReg(reg_idx); } 359 360 FloatReg readFloatReg(int reg_idx, int width) 361 { return actualTC->readFloatReg(reg_idx, width); } 362 363 FloatReg readFloatReg(int reg_idx) 364 { return actualTC->readFloatReg(reg_idx); } 365 366 FloatRegBits readFloatRegBits(int reg_idx, int width) 367 { return actualTC->readFloatRegBits(reg_idx, width); } 368 369 FloatRegBits readFloatRegBits(int reg_idx) 370 { return actualTC->readFloatRegBits(reg_idx); } 371 372 void setIntReg(int reg_idx, uint64_t val) 373 { actualTC->setIntReg(reg_idx, val); } 374 375 void setFloatReg(int reg_idx, FloatReg val, int width) 376 { actualTC->setFloatReg(reg_idx, val, width); } 377 378 void setFloatReg(int reg_idx, FloatReg val) 379 { actualTC->setFloatReg(reg_idx, val); } 380 381 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 382 { actualTC->setFloatRegBits(reg_idx, val, width); } 383 384 void setFloatRegBits(int reg_idx, FloatRegBits val) 385 { actualTC->setFloatRegBits(reg_idx, val); } 386 387 uint64_t readPC() { return actualTC->readPC(); } 388 389 void setPC(uint64_t val) { actualTC->setPC(val); } 390 391 uint64_t readNextPC() { return actualTC->readNextPC(); } 392 393 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 394 395 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 396 397 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 398 399 MiscReg readMiscReg(int misc_reg) 400 { return actualTC->readMiscReg(misc_reg); } 401 402 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 403 { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 404 405 Fault setMiscReg(int misc_reg, const MiscReg &val) 406 { return actualTC->setMiscReg(misc_reg, val); } 407 408 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 409 { return actualTC->setMiscRegWithEffect(misc_reg, val); } 410 411 unsigned readStCondFailures() 412 { return actualTC->readStCondFailures(); } 413 414 void setStCondFailures(unsigned sc_failures) 415 { actualTC->setStCondFailures(sc_failures); } 416#if FULL_SYSTEM 417 bool inPalMode() { return actualTC->inPalMode(); } 418#endif 419 420 // @todo: Fix this! 421 bool misspeculating() { return actualTC->misspeculating(); } 422 423#if !FULL_SYSTEM 424 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 425 426 // used to shift args for indirect syscall 427 void setSyscallArg(int i, IntReg val) 428 { actualTC->setSyscallArg(i, val); } 429 430 void setSyscallReturn(SyscallReturn return_value) 431 { actualTC->setSyscallReturn(return_value); } 432 433 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 434#endif 435 436 void changeRegFileContext(RegFile::ContextParam param, 437 RegFile::ContextVal val) 438 { 439 actualTC->changeRegFileContext(param, val); 440 } 441}; 442 443#endif 444