thread_context.hh revision 14022:a7cdc33dab35 
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_THREAD_CONTEXT_HH__
45#define __CPU_THREAD_CONTEXT_HH__
46
47#include <iostream>
48#include <string>
49
50#include "arch/registers.hh"
51#include "arch/types.hh"
52#include "base/types.hh"
53#include "config/the_isa.hh"
54#include "cpu/reg_class.hh"
55
56// @todo: Figure out a more architecture independent way to obtain the ITB and
57// DTB pointers.
58namespace TheISA
59{
60    class ISA;
61    class Decoder;
62}
63class BaseCPU;
64class BaseTLB;
65class CheckerCPU;
66class Checkpoint;
67class EndQuiesceEvent;
68class PortProxy;
69class Process;
70class System;
71namespace Kernel {
72    class Statistics;
73}
74
75/**
76 * ThreadContext is the external interface to all thread state for
77 * anything outside of the CPU. It provides all accessor methods to
78 * state that might be needed by external objects, ranging from
79 * register values to things such as kernel stats. It is an abstract
80 * base class; the CPU can create its own ThreadContext by
81 * deriving from it.
82 *
83 * The ThreadContext is slightly different than the ExecContext.  The
84 * ThreadContext provides access to an individual thread's state; an
85 * ExecContext provides ISA access to the CPU (meaning it is
86 * implicitly multithreaded on SMT systems).  Additionally the
87 * ThreadState is an abstract class that exactly defines the
88 * interface; the ExecContext is a more implicit interface that must
89 * be implemented so that the ISA can access whatever state it needs.
90 */
91class ThreadContext
92{
93  protected:
94    typedef TheISA::MachInst MachInst;
95    using VecRegContainer = TheISA::VecRegContainer;
96    using VecElem = TheISA::VecElem;
97    using VecPredRegContainer = TheISA::VecPredRegContainer;
98
99  public:
100
101    enum Status
102    {
103        /// Running.  Instructions should be executed only when
104        /// the context is in this state.
105        Active,
106
107        /// Temporarily inactive.  Entered while waiting for
108        /// synchronization, etc.
109        Suspended,
110
111        /// Trying to exit and waiting for an event to completely exit.
112        /// Entered when target executes an exit syscall.
113        Halting,
114
115        /// Permanently shut down.  Entered when target executes
116        /// m5exit pseudo-instruction.  When all contexts enter
117        /// this state, the simulation will terminate.
118        Halted
119    };
120
121    virtual ~ThreadContext() { };
122
123    virtual BaseCPU *getCpuPtr() = 0;
124
125    virtual int cpuId() const = 0;
126
127    virtual uint32_t socketId() const = 0;
128
129    virtual int threadId() const = 0;
130
131    virtual void setThreadId(int id) = 0;
132
133    virtual ContextID contextId() const = 0;
134
135    virtual void setContextId(ContextID id) = 0;
136
137    virtual BaseTLB *getITBPtr() = 0;
138
139    virtual BaseTLB *getDTBPtr() = 0;
140
141    virtual CheckerCPU *getCheckerCpuPtr() = 0;
142
143    virtual TheISA::ISA *getIsaPtr() = 0;
144
145    virtual TheISA::Decoder *getDecoderPtr() = 0;
146
147    virtual System *getSystemPtr() = 0;
148
149    virtual ::Kernel::Statistics *getKernelStats() = 0;
150
151    virtual PortProxy &getPhysProxy() = 0;
152
153    virtual PortProxy &getVirtProxy() = 0;
154
155    /**
156     * Initialise the physical and virtual port proxies and tie them to
157     * the data port of the CPU.
158     *
159     * tc ThreadContext for the virtual-to-physical translation
160     */
161    virtual void initMemProxies(ThreadContext *tc) = 0;
162
163    virtual PortProxy &getMemProxy() = 0;
164
165    virtual Process *getProcessPtr() = 0;
166
167    virtual void setProcessPtr(Process *p) = 0;
168
169    virtual Status status() const = 0;
170
171    virtual void setStatus(Status new_status) = 0;
172
173    /// Set the status to Active.
174    virtual void activate() = 0;
175
176    /// Set the status to Suspended.
177    virtual void suspend() = 0;
178
179    /// Set the status to Halted.
180    virtual void halt() = 0;
181
182    /// Quiesce thread context
183    void quiesce();
184
185    /// Quiesce, suspend, and schedule activate at resume
186    void quiesceTick(Tick resume);
187
188    virtual void dumpFuncProfile() = 0;
189
190    virtual void takeOverFrom(ThreadContext *old_context) = 0;
191
192    virtual void regStats(const std::string &name) = 0;
193
194    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
195
196    // Not necessarily the best location for these...
197    // Having an extra function just to read these is obnoxious
198    virtual Tick readLastActivate() = 0;
199    virtual Tick readLastSuspend() = 0;
200
201    virtual void profileClear() = 0;
202    virtual void profileSample() = 0;
203
204    virtual void copyArchRegs(ThreadContext *tc) = 0;
205
206    virtual void clearArchRegs() = 0;
207
208    //
209    // New accessors for new decoder.
210    //
211    virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
212
213    virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
214
215    virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
216    virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
217
218    /** Vector Register Lane Interfaces. */
219    /** @{ */
220    /** Reads source vector 8bit operand. */
221    virtual ConstVecLane8
222    readVec8BitLaneReg(const RegId& reg) const = 0;
223
224    /** Reads source vector 16bit operand. */
225    virtual ConstVecLane16
226    readVec16BitLaneReg(const RegId& reg) const = 0;
227
228    /** Reads source vector 32bit operand. */
229    virtual ConstVecLane32
230    readVec32BitLaneReg(const RegId& reg) const = 0;
231
232    /** Reads source vector 64bit operand. */
233    virtual ConstVecLane64
234    readVec64BitLaneReg(const RegId& reg) const = 0;
235
236    /** Write a lane of the destination vector register. */
237    virtual void setVecLane(const RegId& reg,
238            const LaneData<LaneSize::Byte>& val) = 0;
239    virtual void setVecLane(const RegId& reg,
240            const LaneData<LaneSize::TwoByte>& val) = 0;
241    virtual void setVecLane(const RegId& reg,
242            const LaneData<LaneSize::FourByte>& val) = 0;
243    virtual void setVecLane(const RegId& reg,
244            const LaneData<LaneSize::EightByte>& val) = 0;
245    /** @} */
246
247    virtual const VecElem& readVecElem(const RegId& reg) const = 0;
248
249    virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
250        const = 0;
251    virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
252
253    virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
254
255    virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
256
257    virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
258
259    virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
260
261    virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
262
263    virtual void setVecPredReg(const RegId& reg,
264                               const VecPredRegContainer& val) = 0;
265
266    virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
267
268    virtual TheISA::PCState pcState() const = 0;
269
270    virtual void pcState(const TheISA::PCState &val) = 0;
271
272    void
273    setNPC(Addr val)
274    {
275        TheISA::PCState pc_state = pcState();
276        pc_state.setNPC(val);
277        pcState(pc_state);
278    }
279
280    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
281
282    virtual Addr instAddr() const = 0;
283
284    virtual Addr nextInstAddr() const = 0;
285
286    virtual MicroPC microPC() const = 0;
287
288    virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
289
290    virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
291
292    virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
293
294    virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
295
296    virtual RegId flattenRegId(const RegId& regId) const = 0;
297
298    // Also not necessarily the best location for these two.  Hopefully will go
299    // away once we decide upon where st cond failures goes.
300    virtual unsigned readStCondFailures() const = 0;
301
302    virtual void setStCondFailures(unsigned sc_failures) = 0;
303
304    // Same with st cond failures.
305    virtual Counter readFuncExeInst() const = 0;
306
307    virtual void syscall(int64_t callnum, Fault *fault) = 0;
308
309    // This function exits the thread context in the CPU and returns
310    // 1 if the CPU has no more active threads (meaning it's OK to exit);
311    // Used in syscall-emulation mode when a  thread calls the exit syscall.
312    virtual int exit() { return 1; };
313
314    /** function to compare two thread contexts (for debugging) */
315    static void compare(ThreadContext *one, ThreadContext *two);
316
317    /** @{ */
318    /**
319     * Flat register interfaces
320     *
321     * Some architectures have different registers visible in
322     * different modes. Such architectures "flatten" a register (see
323     * flattenRegId()) to map it into the
324     * gem5 register file. This interface provides a flat interface to
325     * the underlying register file, which allows for example
326     * serialization code to access all registers.
327     */
328
329    virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
330    virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
331
332    virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
333    virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
334
335    virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
336    virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
337    virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
338
339    virtual const VecElem& readVecElemFlat(RegIndex idx,
340                                           const ElemIndex& elemIdx) const = 0;
341    virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
342                                const VecElem& val) = 0;
343
344    virtual const VecPredRegContainer &
345        readVecPredRegFlat(RegIndex idx) const = 0;
346    virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
347    virtual void setVecPredRegFlat(RegIndex idx,
348                                   const VecPredRegContainer& val) = 0;
349
350    virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
351    virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
352    /** @} */
353
354};
355
356/** @{ */
357/**
358 * Thread context serialization helpers
359 *
360 * These helper functions provide a way to the data in a
361 * ThreadContext. They are provided as separate helper function since
362 * implementing them as members of the ThreadContext interface would
363 * be confusing when the ThreadContext is exported via a proxy.
364 */
365
366void serialize(const ThreadContext &tc, CheckpointOut &cp);
367void unserialize(ThreadContext &tc, CheckpointIn &cp);
368
369/** @} */
370
371
372/**
373 * Copy state between thread contexts in preparation for CPU handover.
374 *
375 * @note This method modifies the old thread contexts as well as the
376 * new thread context. The old thread context will have its quiesce
377 * event descheduled if it is scheduled and its status set to halted.
378 *
379 * @param new_tc Destination ThreadContext.
380 * @param old_tc Source ThreadContext.
381 */
382void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
383
384#endif
385