thread_context.hh revision 13641
112027Sjungma@eit.uni-kl.de/* 212027Sjungma@eit.uni-kl.de * Copyright (c) 2011-2012, 2016-2018 ARM Limited 312027Sjungma@eit.uni-kl.de * Copyright (c) 2013 Advanced Micro Devices, Inc. 412027Sjungma@eit.uni-kl.de * All rights reserved 512027Sjungma@eit.uni-kl.de * 612027Sjungma@eit.uni-kl.de * The license below extends only to copyright in the software and shall 712027Sjungma@eit.uni-kl.de * not be construed as granting a license to any other intellectual 812027Sjungma@eit.uni-kl.de * property including but not limited to intellectual property relating 912027Sjungma@eit.uni-kl.de * to a hardware implementation of the functionality of the software 1012027Sjungma@eit.uni-kl.de * licensed hereunder. You may use the software subject to the license 1112027Sjungma@eit.uni-kl.de * terms below provided that you ensure that this notice is replicated 1212027Sjungma@eit.uni-kl.de * unmodified and in its entirety in all distributions of the software, 1312027Sjungma@eit.uni-kl.de * modified or unmodified, in source code or in binary form. 1412027Sjungma@eit.uni-kl.de * 1512027Sjungma@eit.uni-kl.de * Copyright (c) 2006 The Regents of The University of Michigan 1612027Sjungma@eit.uni-kl.de * All rights reserved. 1712027Sjungma@eit.uni-kl.de * 1812027Sjungma@eit.uni-kl.de * Redistribution and use in source and binary forms, with or without 1912027Sjungma@eit.uni-kl.de * modification, are permitted provided that the following conditions are 2012027Sjungma@eit.uni-kl.de * met: redistributions of source code must retain the above copyright 2112027Sjungma@eit.uni-kl.de * notice, this list of conditions and the following disclaimer; 2212027Sjungma@eit.uni-kl.de * redistributions in binary form must reproduce the above copyright 2312027Sjungma@eit.uni-kl.de * notice, this list of conditions and the following disclaimer in the 2412027Sjungma@eit.uni-kl.de * documentation and/or other materials provided with the distribution; 2512027Sjungma@eit.uni-kl.de * neither the name of the copyright holders nor the names of its 2612027Sjungma@eit.uni-kl.de * contributors may be used to endorse or promote products derived from 2712027Sjungma@eit.uni-kl.de * this software without specific prior written permission. 2812027Sjungma@eit.uni-kl.de * 2912027Sjungma@eit.uni-kl.de * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012027Sjungma@eit.uni-kl.de * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112027Sjungma@eit.uni-kl.de * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212027Sjungma@eit.uni-kl.de * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3312027Sjungma@eit.uni-kl.de * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3412027Sjungma@eit.uni-kl.de * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3512027Sjungma@eit.uni-kl.de * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612027Sjungma@eit.uni-kl.de * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712027Sjungma@eit.uni-kl.de * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812027Sjungma@eit.uni-kl.de * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3912027Sjungma@eit.uni-kl.de * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012027Sjungma@eit.uni-kl.de * 4112027Sjungma@eit.uni-kl.de * Authors: Kevin Lim 4212027Sjungma@eit.uni-kl.de */ 4312027Sjungma@eit.uni-kl.de 4412027Sjungma@eit.uni-kl.de#ifndef __CPU_THREAD_CONTEXT_HH__ 4512027Sjungma@eit.uni-kl.de#define __CPU_THREAD_CONTEXT_HH__ 4612027Sjungma@eit.uni-kl.de 4712027Sjungma@eit.uni-kl.de#include <iostream> 4812027Sjungma@eit.uni-kl.de#include <string> 4912027Sjungma@eit.uni-kl.de 5012027Sjungma@eit.uni-kl.de#include "arch/registers.hh" 5112027Sjungma@eit.uni-kl.de#include "arch/types.hh" 5212027Sjungma@eit.uni-kl.de#include "base/types.hh" 5312027Sjungma@eit.uni-kl.de#include "config/the_isa.hh" 5412027Sjungma@eit.uni-kl.de#include "cpu/reg_class.hh" 5512027Sjungma@eit.uni-kl.de 5612027Sjungma@eit.uni-kl.de// @todo: Figure out a more architecture independent way to obtain the ITB and 5712027Sjungma@eit.uni-kl.de// DTB pointers. 5812027Sjungma@eit.uni-kl.denamespace TheISA 5912027Sjungma@eit.uni-kl.de{ 6012027Sjungma@eit.uni-kl.de class Decoder; 6112027Sjungma@eit.uni-kl.de} 6212027Sjungma@eit.uni-kl.declass BaseCPU; 6312027Sjungma@eit.uni-kl.declass BaseTLB; 6412027Sjungma@eit.uni-kl.declass CheckerCPU; 6512027Sjungma@eit.uni-kl.declass Checkpoint; 6612027Sjungma@eit.uni-kl.declass EndQuiesceEvent; 6712027Sjungma@eit.uni-kl.declass SETranslatingPortProxy; 6812027Sjungma@eit.uni-kl.declass FSTranslatingPortProxy; 6912027Sjungma@eit.uni-kl.declass PortProxy; 7012027Sjungma@eit.uni-kl.declass Process; 7112027Sjungma@eit.uni-kl.declass System; 7212027Sjungma@eit.uni-kl.denamespace TheISA { 7312027Sjungma@eit.uni-kl.de namespace Kernel { 7412027Sjungma@eit.uni-kl.de class Statistics; 7512027Sjungma@eit.uni-kl.de } 7612027Sjungma@eit.uni-kl.de} 7712027Sjungma@eit.uni-kl.de 7812027Sjungma@eit.uni-kl.de/** 7912027Sjungma@eit.uni-kl.de * ThreadContext is the external interface to all thread state for 8012027Sjungma@eit.uni-kl.de * anything outside of the CPU. It provides all accessor methods to 8112027Sjungma@eit.uni-kl.de * state that might be needed by external objects, ranging from 8212027Sjungma@eit.uni-kl.de * register values to things such as kernel stats. It is an abstract 8312027Sjungma@eit.uni-kl.de * base class; the CPU can create its own ThreadContext by either 8412027Sjungma@eit.uni-kl.de * deriving from it, or using the templated ProxyThreadContext. 8512027Sjungma@eit.uni-kl.de * 8612027Sjungma@eit.uni-kl.de * The ThreadContext is slightly different than the ExecContext. The 8712027Sjungma@eit.uni-kl.de * ThreadContext provides access to an individual thread's state; an 8812027Sjungma@eit.uni-kl.de * ExecContext provides ISA access to the CPU (meaning it is 8912027Sjungma@eit.uni-kl.de * implicitly multithreaded on SMT systems). Additionally the 9012027Sjungma@eit.uni-kl.de * ThreadState is an abstract class that exactly defines the 9112027Sjungma@eit.uni-kl.de * interface; the ExecContext is a more implicit interface that must 9212027Sjungma@eit.uni-kl.de * be implemented so that the ISA can access whatever state it needs. 9312027Sjungma@eit.uni-kl.de */ 9412027Sjungma@eit.uni-kl.declass ThreadContext 9512027Sjungma@eit.uni-kl.de{ 9612027Sjungma@eit.uni-kl.de protected: 9712027Sjungma@eit.uni-kl.de typedef TheISA::MachInst MachInst; 9812027Sjungma@eit.uni-kl.de using VecRegContainer = TheISA::VecRegContainer; 9912027Sjungma@eit.uni-kl.de using VecElem = TheISA::VecElem; 10012027Sjungma@eit.uni-kl.de using VecPredRegContainer = TheISA::VecPredRegContainer; 10112027Sjungma@eit.uni-kl.de 10212027Sjungma@eit.uni-kl.de public: 10312027Sjungma@eit.uni-kl.de 10412027Sjungma@eit.uni-kl.de enum Status 10512027Sjungma@eit.uni-kl.de { 10612027Sjungma@eit.uni-kl.de /// Running. Instructions should be executed only when 10712027Sjungma@eit.uni-kl.de /// the context is in this state. 10812027Sjungma@eit.uni-kl.de Active, 10912027Sjungma@eit.uni-kl.de 11012027Sjungma@eit.uni-kl.de /// Temporarily inactive. Entered while waiting for 11112027Sjungma@eit.uni-kl.de /// synchronization, etc. 11212027Sjungma@eit.uni-kl.de Suspended, 11312027Sjungma@eit.uni-kl.de 11412027Sjungma@eit.uni-kl.de /// Trying to exit and waiting for an event to completely exit. 11512027Sjungma@eit.uni-kl.de /// Entered when target executes an exit syscall. 11612027Sjungma@eit.uni-kl.de Halting, 11712027Sjungma@eit.uni-kl.de 11812027Sjungma@eit.uni-kl.de /// Permanently shut down. Entered when target executes 11912027Sjungma@eit.uni-kl.de /// m5exit pseudo-instruction. When all contexts enter 12012027Sjungma@eit.uni-kl.de /// this state, the simulation will terminate. 12112027Sjungma@eit.uni-kl.de Halted 12212027Sjungma@eit.uni-kl.de }; 12312027Sjungma@eit.uni-kl.de 12412027Sjungma@eit.uni-kl.de virtual ~ThreadContext() { }; 12512027Sjungma@eit.uni-kl.de 12612027Sjungma@eit.uni-kl.de virtual BaseCPU *getCpuPtr() = 0; 12712027Sjungma@eit.uni-kl.de 12812027Sjungma@eit.uni-kl.de virtual int cpuId() const = 0; 12912027Sjungma@eit.uni-kl.de 13012027Sjungma@eit.uni-kl.de virtual uint32_t socketId() const = 0; 13112027Sjungma@eit.uni-kl.de 13212027Sjungma@eit.uni-kl.de virtual int threadId() const = 0; 13312027Sjungma@eit.uni-kl.de 13412027Sjungma@eit.uni-kl.de virtual void setThreadId(int id) = 0; 13512027Sjungma@eit.uni-kl.de 13612027Sjungma@eit.uni-kl.de virtual int contextId() const = 0; 13712027Sjungma@eit.uni-kl.de 13812027Sjungma@eit.uni-kl.de virtual void setContextId(int id) = 0; 13912027Sjungma@eit.uni-kl.de 14012027Sjungma@eit.uni-kl.de virtual BaseTLB *getITBPtr() = 0; 14112027Sjungma@eit.uni-kl.de 14212027Sjungma@eit.uni-kl.de virtual BaseTLB *getDTBPtr() = 0; 14312027Sjungma@eit.uni-kl.de 14412027Sjungma@eit.uni-kl.de virtual CheckerCPU *getCheckerCpuPtr() = 0; 14512027Sjungma@eit.uni-kl.de 14612027Sjungma@eit.uni-kl.de virtual TheISA::Decoder *getDecoderPtr() = 0; 14712027Sjungma@eit.uni-kl.de 14812027Sjungma@eit.uni-kl.de virtual System *getSystemPtr() = 0; 14912027Sjungma@eit.uni-kl.de 15012027Sjungma@eit.uni-kl.de virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 15112027Sjungma@eit.uni-kl.de 15212027Sjungma@eit.uni-kl.de virtual PortProxy &getPhysProxy() = 0; 15312027Sjungma@eit.uni-kl.de 15412027Sjungma@eit.uni-kl.de virtual FSTranslatingPortProxy &getVirtProxy() = 0; 15512027Sjungma@eit.uni-kl.de 15612027Sjungma@eit.uni-kl.de /** 15712027Sjungma@eit.uni-kl.de * Initialise the physical and virtual port proxies and tie them to 15812027Sjungma@eit.uni-kl.de * the data port of the CPU. 15912027Sjungma@eit.uni-kl.de * 16012027Sjungma@eit.uni-kl.de * tc ThreadContext for the virtual-to-physical translation 16112027Sjungma@eit.uni-kl.de */ 16212027Sjungma@eit.uni-kl.de virtual void initMemProxies(ThreadContext *tc) = 0; 16312027Sjungma@eit.uni-kl.de 16412027Sjungma@eit.uni-kl.de virtual SETranslatingPortProxy &getMemProxy() = 0; 16512027Sjungma@eit.uni-kl.de 16612027Sjungma@eit.uni-kl.de virtual Process *getProcessPtr() = 0; 16712027Sjungma@eit.uni-kl.de 16812027Sjungma@eit.uni-kl.de virtual void setProcessPtr(Process *p) = 0; 16912027Sjungma@eit.uni-kl.de 17012027Sjungma@eit.uni-kl.de virtual Status status() const = 0; 17112027Sjungma@eit.uni-kl.de 17212027Sjungma@eit.uni-kl.de virtual void setStatus(Status new_status) = 0; 17312027Sjungma@eit.uni-kl.de 17412027Sjungma@eit.uni-kl.de /// Set the status to Active. 17512027Sjungma@eit.uni-kl.de virtual void activate() = 0; 17612027Sjungma@eit.uni-kl.de 17712027Sjungma@eit.uni-kl.de /// Set the status to Suspended. 17812027Sjungma@eit.uni-kl.de virtual void suspend() = 0; 17912027Sjungma@eit.uni-kl.de 18012027Sjungma@eit.uni-kl.de /// Set the status to Halted. 18112027Sjungma@eit.uni-kl.de virtual void halt() = 0; 18212027Sjungma@eit.uni-kl.de 18312027Sjungma@eit.uni-kl.de /// Quiesce thread context 18412027Sjungma@eit.uni-kl.de void quiesce(); 18512027Sjungma@eit.uni-kl.de 18612027Sjungma@eit.uni-kl.de /// Quiesce, suspend, and schedule activate at resume 18712027Sjungma@eit.uni-kl.de void quiesceTick(Tick resume); 18812027Sjungma@eit.uni-kl.de 18912027Sjungma@eit.uni-kl.de virtual void dumpFuncProfile() = 0; 19012027Sjungma@eit.uni-kl.de 19112027Sjungma@eit.uni-kl.de virtual void takeOverFrom(ThreadContext *old_context) = 0; 192 193 virtual void regStats(const std::string &name) = 0; 194 195 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 196 197 // Not necessarily the best location for these... 198 // Having an extra function just to read these is obnoxious 199 virtual Tick readLastActivate() = 0; 200 virtual Tick readLastSuspend() = 0; 201 202 virtual void profileClear() = 0; 203 virtual void profileSample() = 0; 204 205 virtual void copyArchRegs(ThreadContext *tc) = 0; 206 207 virtual void clearArchRegs() = 0; 208 209 // 210 // New accessors for new decoder. 211 // 212 virtual RegVal readIntReg(int reg_idx) = 0; 213 214 virtual RegVal readFloatReg(int reg_idx) = 0; 215 216 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 217 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 218 219 /** Vector Register Lane Interfaces. */ 220 /** @{ */ 221 /** Reads source vector 8bit operand. */ 222 virtual ConstVecLane8 223 readVec8BitLaneReg(const RegId& reg) const = 0; 224 225 /** Reads source vector 16bit operand. */ 226 virtual ConstVecLane16 227 readVec16BitLaneReg(const RegId& reg) const = 0; 228 229 /** Reads source vector 32bit operand. */ 230 virtual ConstVecLane32 231 readVec32BitLaneReg(const RegId& reg) const = 0; 232 233 /** Reads source vector 64bit operand. */ 234 virtual ConstVecLane64 235 readVec64BitLaneReg(const RegId& reg) const = 0; 236 237 /** Write a lane of the destination vector register. */ 238 virtual void setVecLane(const RegId& reg, 239 const LaneData<LaneSize::Byte>& val) = 0; 240 virtual void setVecLane(const RegId& reg, 241 const LaneData<LaneSize::TwoByte>& val) = 0; 242 virtual void setVecLane(const RegId& reg, 243 const LaneData<LaneSize::FourByte>& val) = 0; 244 virtual void setVecLane(const RegId& reg, 245 const LaneData<LaneSize::EightByte>& val) = 0; 246 /** @} */ 247 248 virtual const VecElem& readVecElem(const RegId& reg) const = 0; 249 250 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg) 251 const = 0; 252 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0; 253 254 virtual RegVal readCCReg(int reg_idx) = 0; 255 256 virtual void setIntReg(int reg_idx, RegVal val) = 0; 257 258 virtual void setFloatReg(int reg_idx, RegVal val) = 0; 259 260 virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 261 262 virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 263 264 virtual void setVecPredReg(const RegId& reg, 265 const VecPredRegContainer& val) = 0; 266 267 virtual void setCCReg(int reg_idx, RegVal val) = 0; 268 269 virtual TheISA::PCState pcState() = 0; 270 271 virtual void pcState(const TheISA::PCState &val) = 0; 272 273 void 274 setNPC(Addr val) 275 { 276 TheISA::PCState pc_state = pcState(); 277 pc_state.setNPC(val); 278 pcState(pc_state); 279 } 280 281 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 282 283 virtual Addr instAddr() = 0; 284 285 virtual Addr nextInstAddr() = 0; 286 287 virtual MicroPC microPC() = 0; 288 289 virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0; 290 291 virtual RegVal readMiscReg(int misc_reg) = 0; 292 293 virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0; 294 295 virtual void setMiscReg(int misc_reg, RegVal val) = 0; 296 297 virtual RegId flattenRegId(const RegId& regId) const = 0; 298 299 virtual RegVal 300 readRegOtherThread(const RegId& misc_reg, ThreadID tid) 301 { 302 return 0; 303 } 304 305 virtual void 306 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) 307 { 308 } 309 310 // Also not necessarily the best location for these two. Hopefully will go 311 // away once we decide upon where st cond failures goes. 312 virtual unsigned readStCondFailures() = 0; 313 314 virtual void setStCondFailures(unsigned sc_failures) = 0; 315 316 // Same with st cond failures. 317 virtual Counter readFuncExeInst() = 0; 318 319 virtual void syscall(int64_t callnum, Fault *fault) = 0; 320 321 // This function exits the thread context in the CPU and returns 322 // 1 if the CPU has no more active threads (meaning it's OK to exit); 323 // Used in syscall-emulation mode when a thread calls the exit syscall. 324 virtual int exit() { return 1; }; 325 326 /** function to compare two thread contexts (for debugging) */ 327 static void compare(ThreadContext *one, ThreadContext *two); 328 329 /** @{ */ 330 /** 331 * Flat register interfaces 332 * 333 * Some architectures have different registers visible in 334 * different modes. Such architectures "flatten" a register (see 335 * flattenRegId()) to map it into the 336 * gem5 register file. This interface provides a flat interface to 337 * the underlying register file, which allows for example 338 * serialization code to access all registers. 339 */ 340 341 virtual RegVal readIntRegFlat(int idx) = 0; 342 virtual void setIntRegFlat(int idx, RegVal val) = 0; 343 344 virtual RegVal readFloatRegFlat(int idx) = 0; 345 virtual void setFloatRegFlat(int idx, RegVal val) = 0; 346 347 virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; 348 virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; 349 virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0; 350 351 virtual const VecElem& readVecElemFlat(const RegIndex& idx, 352 const ElemIndex& elemIdx) const = 0; 353 virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, 354 const VecElem& val) = 0; 355 356 virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0; 357 virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0; 358 virtual void setVecPredRegFlat(int idx, 359 const VecPredRegContainer& val) = 0; 360 361 virtual RegVal readCCRegFlat(int idx) = 0; 362 virtual void setCCRegFlat(int idx, RegVal val) = 0; 363 /** @} */ 364 365}; 366 367/** 368 * ProxyThreadContext class that provides a way to implement a 369 * ThreadContext without having to derive from it. ThreadContext is an 370 * abstract class, so anything that derives from it and uses its 371 * interface will pay the overhead of virtual function calls. This 372 * class is created to enable a user-defined Thread object to be used 373 * wherever ThreadContexts are used, without paying the overhead of 374 * virtual function calls when it is used by itself. See 375 * simple_thread.hh for an example of this. 376 */ 377template <class TC> 378class ProxyThreadContext : public ThreadContext 379{ 380 public: 381 ProxyThreadContext(TC *actual_tc) 382 { actualTC = actual_tc; } 383 384 private: 385 TC *actualTC; 386 387 public: 388 389 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 390 391 int cpuId() const { return actualTC->cpuId(); } 392 393 uint32_t socketId() const { return actualTC->socketId(); } 394 395 int threadId() const { return actualTC->threadId(); } 396 397 void setThreadId(int id) { actualTC->setThreadId(id); } 398 399 int contextId() const { return actualTC->contextId(); } 400 401 void setContextId(int id) { actualTC->setContextId(id); } 402 403 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 404 405 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 406 407 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 408 409 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 410 411 System *getSystemPtr() { return actualTC->getSystemPtr(); } 412 413 TheISA::Kernel::Statistics *getKernelStats() 414 { return actualTC->getKernelStats(); } 415 416 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 417 418 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 419 420 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 421 422 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 423 424 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 425 426 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 427 428 Status status() const { return actualTC->status(); } 429 430 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 431 432 /// Set the status to Active. 433 void activate() { actualTC->activate(); } 434 435 /// Set the status to Suspended. 436 void suspend() { actualTC->suspend(); } 437 438 /// Set the status to Halted. 439 void halt() { actualTC->halt(); } 440 441 /// Quiesce thread context 442 void quiesce() { actualTC->quiesce(); } 443 444 /// Quiesce, suspend, and schedule activate at resume 445 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); } 446 447 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 448 449 void takeOverFrom(ThreadContext *oldContext) 450 { actualTC->takeOverFrom(oldContext); } 451 452 void regStats(const std::string &name) { actualTC->regStats(name); } 453 454 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 455 456 Tick readLastActivate() { return actualTC->readLastActivate(); } 457 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 458 459 void profileClear() { return actualTC->profileClear(); } 460 void profileSample() { return actualTC->profileSample(); } 461 462 // @todo: Do I need this? 463 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 464 465 void clearArchRegs() { actualTC->clearArchRegs(); } 466 467 // 468 // New accessors for new decoder. 469 // 470 RegVal readIntReg(int reg_idx) 471 { return actualTC->readIntReg(reg_idx); } 472 473 RegVal readFloatReg(int reg_idx) 474 { return actualTC->readFloatReg(reg_idx); } 475 476 const VecRegContainer& readVecReg(const RegId& reg) const 477 { return actualTC->readVecReg(reg); } 478 479 VecRegContainer& getWritableVecReg(const RegId& reg) 480 { return actualTC->getWritableVecReg(reg); } 481 482 /** Vector Register Lane Interfaces. */ 483 /** @{ */ 484 /** Reads source vector 8bit operand. */ 485 ConstVecLane8 486 readVec8BitLaneReg(const RegId& reg) const 487 { return actualTC->readVec8BitLaneReg(reg); } 488 489 /** Reads source vector 16bit operand. */ 490 ConstVecLane16 491 readVec16BitLaneReg(const RegId& reg) const 492 { return actualTC->readVec16BitLaneReg(reg); } 493 494 /** Reads source vector 32bit operand. */ 495 ConstVecLane32 496 readVec32BitLaneReg(const RegId& reg) const 497 { return actualTC->readVec32BitLaneReg(reg); } 498 499 /** Reads source vector 64bit operand. */ 500 ConstVecLane64 501 readVec64BitLaneReg(const RegId& reg) const 502 { return actualTC->readVec64BitLaneReg(reg); } 503 504 /** Write a lane of the destination vector register. */ 505 virtual void setVecLane(const RegId& reg, 506 const LaneData<LaneSize::Byte>& val) 507 { return actualTC->setVecLane(reg, val); } 508 virtual void setVecLane(const RegId& reg, 509 const LaneData<LaneSize::TwoByte>& val) 510 { return actualTC->setVecLane(reg, val); } 511 virtual void setVecLane(const RegId& reg, 512 const LaneData<LaneSize::FourByte>& val) 513 { return actualTC->setVecLane(reg, val); } 514 virtual void setVecLane(const RegId& reg, 515 const LaneData<LaneSize::EightByte>& val) 516 { return actualTC->setVecLane(reg, val); } 517 /** @} */ 518 519 const VecElem& readVecElem(const RegId& reg) const 520 { return actualTC->readVecElem(reg); } 521 522 const VecPredRegContainer& readVecPredReg(const RegId& reg) const 523 { return actualTC->readVecPredReg(reg); } 524 525 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) 526 { return actualTC->getWritableVecPredReg(reg); } 527 528 RegVal readCCReg(int reg_idx) 529 { return actualTC->readCCReg(reg_idx); } 530 531 void setIntReg(int reg_idx, RegVal val) 532 { actualTC->setIntReg(reg_idx, val); } 533 534 void setFloatReg(int reg_idx, RegVal val) 535 { actualTC->setFloatReg(reg_idx, val); } 536 537 void setVecReg(const RegId& reg, const VecRegContainer& val) 538 { actualTC->setVecReg(reg, val); } 539 540 void setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 541 { actualTC->setVecPredReg(reg, val); } 542 543 void setVecElem(const RegId& reg, const VecElem& val) 544 { actualTC->setVecElem(reg, val); } 545 546 void setCCReg(int reg_idx, RegVal val) 547 { actualTC->setCCReg(reg_idx, val); } 548 549 TheISA::PCState pcState() { return actualTC->pcState(); } 550 551 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 552 553 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 554 555 Addr instAddr() { return actualTC->instAddr(); } 556 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 557 MicroPC microPC() { return actualTC->microPC(); } 558 559 bool readPredicate() { return actualTC->readPredicate(); } 560 561 void setPredicate(bool val) 562 { actualTC->setPredicate(val); } 563 564 RegVal readMiscRegNoEffect(int misc_reg) const 565 { return actualTC->readMiscRegNoEffect(misc_reg); } 566 567 RegVal readMiscReg(int misc_reg) 568 { return actualTC->readMiscReg(misc_reg); } 569 570 void setMiscRegNoEffect(int misc_reg, RegVal val) 571 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 572 573 void setMiscReg(int misc_reg, RegVal val) 574 { return actualTC->setMiscReg(misc_reg, val); } 575 576 RegId flattenRegId(const RegId& regId) const 577 { return actualTC->flattenRegId(regId); } 578 579 unsigned readStCondFailures() 580 { return actualTC->readStCondFailures(); } 581 582 void setStCondFailures(unsigned sc_failures) 583 { actualTC->setStCondFailures(sc_failures); } 584 585 void syscall(int64_t callnum, Fault *fault) 586 { actualTC->syscall(callnum, fault); } 587 588 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 589 590 RegVal readIntRegFlat(int idx) 591 { return actualTC->readIntRegFlat(idx); } 592 593 void setIntRegFlat(int idx, RegVal val) 594 { actualTC->setIntRegFlat(idx, val); } 595 596 RegVal readFloatRegFlat(int idx) 597 { return actualTC->readFloatRegFlat(idx); } 598 599 void setFloatRegFlat(int idx, RegVal val) 600 { actualTC->setFloatRegFlat(idx, val); } 601 602 const VecRegContainer& readVecRegFlat(int id) const 603 { return actualTC->readVecRegFlat(id); } 604 605 VecRegContainer& getWritableVecRegFlat(int id) 606 { return actualTC->getWritableVecRegFlat(id); } 607 608 void setVecRegFlat(int idx, const VecRegContainer& val) 609 { actualTC->setVecRegFlat(idx, val); } 610 611 const VecElem& readVecElemFlat(const RegIndex& id, 612 const ElemIndex& elemIndex) const 613 { return actualTC->readVecElemFlat(id, elemIndex); } 614 615 void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex, 616 const VecElem& val) 617 { actualTC->setVecElemFlat(id, elemIndex, val); } 618 619 const VecPredRegContainer& readVecPredRegFlat(int id) const 620 { return actualTC->readVecPredRegFlat(id); } 621 622 VecPredRegContainer& getWritableVecPredRegFlat(int id) 623 { return actualTC->getWritableVecPredRegFlat(id); } 624 625 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) 626 { actualTC->setVecPredRegFlat(idx, val); } 627 628 RegVal readCCRegFlat(int idx) 629 { return actualTC->readCCRegFlat(idx); } 630 631 void setCCRegFlat(int idx, RegVal val) 632 { actualTC->setCCRegFlat(idx, val); } 633}; 634 635/** @{ */ 636/** 637 * Thread context serialization helpers 638 * 639 * These helper functions provide a way to the data in a 640 * ThreadContext. They are provided as separate helper function since 641 * implementing them as members of the ThreadContext interface would 642 * be confusing when the ThreadContext is exported via a proxy. 643 */ 644 645void serialize(ThreadContext &tc, CheckpointOut &cp); 646void unserialize(ThreadContext &tc, CheckpointIn &cp); 647 648/** @} */ 649 650 651/** 652 * Copy state between thread contexts in preparation for CPU handover. 653 * 654 * @note This method modifies the old thread contexts as well as the 655 * new thread context. The old thread context will have its quiesce 656 * event descheduled if it is scheduled and its status set to halted. 657 * 658 * @param new_tc Destination ThreadContext. 659 * @param old_tc Source ThreadContext. 660 */ 661void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 662 663#endif 664