thread_context.hh revision 12106:7784fac1b159
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_THREAD_CONTEXT_HH__ 45#define __CPU_THREAD_CONTEXT_HH__ 46 47#include <iostream> 48#include <string> 49 50#include "arch/registers.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" 54#include "cpu/reg_class.hh" 55 56// @todo: Figure out a more architecture independent way to obtain the ITB and 57// DTB pointers. 58namespace TheISA 59{ 60 class Decoder; 61 class TLB; 62} 63class BaseCPU; 64class CheckerCPU; 65class Checkpoint; 66class EndQuiesceEvent; 67class SETranslatingPortProxy; 68class FSTranslatingPortProxy; 69class PortProxy; 70class Process; 71class System; 72namespace TheISA { 73 namespace Kernel { 74 class Statistics; 75 } 76} 77 78/** 79 * ThreadContext is the external interface to all thread state for 80 * anything outside of the CPU. It provides all accessor methods to 81 * state that might be needed by external objects, ranging from 82 * register values to things such as kernel stats. It is an abstract 83 * base class; the CPU can create its own ThreadContext by either 84 * deriving from it, or using the templated ProxyThreadContext. 85 * 86 * The ThreadContext is slightly different than the ExecContext. The 87 * ThreadContext provides access to an individual thread's state; an 88 * ExecContext provides ISA access to the CPU (meaning it is 89 * implicitly multithreaded on SMT systems). Additionally the 90 * ThreadState is an abstract class that exactly defines the 91 * interface; the ExecContext is a more implicit interface that must 92 * be implemented so that the ISA can access whatever state it needs. 93 */ 94class ThreadContext 95{ 96 protected: 97 typedef TheISA::MachInst MachInst; 98 typedef TheISA::IntReg IntReg; 99 typedef TheISA::FloatReg FloatReg; 100 typedef TheISA::FloatRegBits FloatRegBits; 101 typedef TheISA::CCReg CCReg; 102 typedef TheISA::MiscReg MiscReg; 103 public: 104 105 enum Status 106 { 107 /// Running. Instructions should be executed only when 108 /// the context is in this state. 109 Active, 110 111 /// Temporarily inactive. Entered while waiting for 112 /// synchronization, etc. 113 Suspended, 114 115 /// Permanently shut down. Entered when target executes 116 /// m5exit pseudo-instruction. When all contexts enter 117 /// this state, the simulation will terminate. 118 Halted 119 }; 120 121 virtual ~ThreadContext() { }; 122 123 virtual BaseCPU *getCpuPtr() = 0; 124 125 virtual int cpuId() const = 0; 126 127 virtual uint32_t socketId() const = 0; 128 129 virtual int threadId() const = 0; 130 131 virtual void setThreadId(int id) = 0; 132 133 virtual int contextId() const = 0; 134 135 virtual void setContextId(int id) = 0; 136 137 virtual TheISA::TLB *getITBPtr() = 0; 138 139 virtual TheISA::TLB *getDTBPtr() = 0; 140 141 virtual CheckerCPU *getCheckerCpuPtr() = 0; 142 143 virtual TheISA::Decoder *getDecoderPtr() = 0; 144 145 virtual System *getSystemPtr() = 0; 146 147 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 148 149 virtual PortProxy &getPhysProxy() = 0; 150 151 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 152 153 /** 154 * Initialise the physical and virtual port proxies and tie them to 155 * the data port of the CPU. 156 * 157 * tc ThreadContext for the virtual-to-physical translation 158 */ 159 virtual void initMemProxies(ThreadContext *tc) = 0; 160 161 virtual SETranslatingPortProxy &getMemProxy() = 0; 162 163 virtual Process *getProcessPtr() = 0; 164 165 virtual void setProcessPtr(Process *p) = 0; 166 167 virtual Status status() const = 0; 168 169 virtual void setStatus(Status new_status) = 0; 170 171 /// Set the status to Active. 172 virtual void activate() = 0; 173 174 /// Set the status to Suspended. 175 virtual void suspend() = 0; 176 177 /// Set the status to Halted. 178 virtual void halt() = 0; 179 180 /// Quiesce thread context 181 void quiesce(); 182 183 /// Quiesce, suspend, and schedule activate at resume 184 void quiesceTick(Tick resume); 185 186 virtual void dumpFuncProfile() = 0; 187 188 virtual void takeOverFrom(ThreadContext *old_context) = 0; 189 190 virtual void regStats(const std::string &name) = 0; 191 192 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 193 194 // Not necessarily the best location for these... 195 // Having an extra function just to read these is obnoxious 196 virtual Tick readLastActivate() = 0; 197 virtual Tick readLastSuspend() = 0; 198 199 virtual void profileClear() = 0; 200 virtual void profileSample() = 0; 201 202 virtual void copyArchRegs(ThreadContext *tc) = 0; 203 204 virtual void clearArchRegs() = 0; 205 206 // 207 // New accessors for new decoder. 208 // 209 virtual uint64_t readIntReg(int reg_idx) = 0; 210 211 virtual FloatReg readFloatReg(int reg_idx) = 0; 212 213 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 214 215 virtual CCReg readCCReg(int reg_idx) = 0; 216 217 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 218 219 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 220 221 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 222 223 virtual void setCCReg(int reg_idx, CCReg val) = 0; 224 225 virtual TheISA::PCState pcState() = 0; 226 227 virtual void pcState(const TheISA::PCState &val) = 0; 228 229 void 230 setNPC(Addr val) 231 { 232 TheISA::PCState pc_state = pcState(); 233 pc_state.setNPC(val); 234 pcState(pc_state); 235 } 236 237 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 238 239 virtual Addr instAddr() = 0; 240 241 virtual Addr nextInstAddr() = 0; 242 243 virtual MicroPC microPC() = 0; 244 245 virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; 246 247 virtual MiscReg readMiscReg(int misc_reg) = 0; 248 249 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 250 251 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 252 253 virtual RegId flattenRegId(const RegId& regId) const = 0; 254 255 virtual uint64_t 256 readRegOtherThread(const RegId& misc_reg, ThreadID tid) 257 { 258 return 0; 259 } 260 261 virtual void 262 setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid) 263 { 264 } 265 266 // Also not necessarily the best location for these two. Hopefully will go 267 // away once we decide upon where st cond failures goes. 268 virtual unsigned readStCondFailures() = 0; 269 270 virtual void setStCondFailures(unsigned sc_failures) = 0; 271 272 // Same with st cond failures. 273 virtual Counter readFuncExeInst() = 0; 274 275 virtual void syscall(int64_t callnum, Fault *fault) = 0; 276 277 // This function exits the thread context in the CPU and returns 278 // 1 if the CPU has no more active threads (meaning it's OK to exit); 279 // Used in syscall-emulation mode when a thread calls the exit syscall. 280 virtual int exit() { return 1; }; 281 282 /** function to compare two thread contexts (for debugging) */ 283 static void compare(ThreadContext *one, ThreadContext *two); 284 285 /** @{ */ 286 /** 287 * Flat register interfaces 288 * 289 * Some architectures have different registers visible in 290 * different modes. Such architectures "flatten" a register (see 291 * flattenRegId()) to map it into the 292 * gem5 register file. This interface provides a flat interface to 293 * the underlying register file, which allows for example 294 * serialization code to access all registers. 295 */ 296 297 virtual uint64_t readIntRegFlat(int idx) = 0; 298 virtual void setIntRegFlat(int idx, uint64_t val) = 0; 299 300 virtual FloatReg readFloatRegFlat(int idx) = 0; 301 virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 302 303 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 304 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 305 306 virtual CCReg readCCRegFlat(int idx) = 0; 307 virtual void setCCRegFlat(int idx, CCReg val) = 0; 308 /** @} */ 309 310}; 311 312/** 313 * ProxyThreadContext class that provides a way to implement a 314 * ThreadContext without having to derive from it. ThreadContext is an 315 * abstract class, so anything that derives from it and uses its 316 * interface will pay the overhead of virtual function calls. This 317 * class is created to enable a user-defined Thread object to be used 318 * wherever ThreadContexts are used, without paying the overhead of 319 * virtual function calls when it is used by itself. See 320 * simple_thread.hh for an example of this. 321 */ 322template <class TC> 323class ProxyThreadContext : public ThreadContext 324{ 325 public: 326 ProxyThreadContext(TC *actual_tc) 327 { actualTC = actual_tc; } 328 329 private: 330 TC *actualTC; 331 332 public: 333 334 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 335 336 int cpuId() const { return actualTC->cpuId(); } 337 338 uint32_t socketId() const { return actualTC->socketId(); } 339 340 int threadId() const { return actualTC->threadId(); } 341 342 void setThreadId(int id) { actualTC->setThreadId(id); } 343 344 int contextId() const { return actualTC->contextId(); } 345 346 void setContextId(int id) { actualTC->setContextId(id); } 347 348 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 349 350 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 351 352 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 353 354 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 355 356 System *getSystemPtr() { return actualTC->getSystemPtr(); } 357 358 TheISA::Kernel::Statistics *getKernelStats() 359 { return actualTC->getKernelStats(); } 360 361 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 362 363 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 364 365 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 366 367 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 368 369 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 370 371 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 372 373 Status status() const { return actualTC->status(); } 374 375 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 376 377 /// Set the status to Active. 378 void activate() { actualTC->activate(); } 379 380 /// Set the status to Suspended. 381 void suspend() { actualTC->suspend(); } 382 383 /// Set the status to Halted. 384 void halt() { actualTC->halt(); } 385 386 /// Quiesce thread context 387 void quiesce() { actualTC->quiesce(); } 388 389 /// Quiesce, suspend, and schedule activate at resume 390 void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); } 391 392 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 393 394 void takeOverFrom(ThreadContext *oldContext) 395 { actualTC->takeOverFrom(oldContext); } 396 397 void regStats(const std::string &name) { actualTC->regStats(name); } 398 399 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 400 401 Tick readLastActivate() { return actualTC->readLastActivate(); } 402 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 403 404 void profileClear() { return actualTC->profileClear(); } 405 void profileSample() { return actualTC->profileSample(); } 406 407 // @todo: Do I need this? 408 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 409 410 void clearArchRegs() { actualTC->clearArchRegs(); } 411 412 // 413 // New accessors for new decoder. 414 // 415 uint64_t readIntReg(int reg_idx) 416 { return actualTC->readIntReg(reg_idx); } 417 418 FloatReg readFloatReg(int reg_idx) 419 { return actualTC->readFloatReg(reg_idx); } 420 421 FloatRegBits readFloatRegBits(int reg_idx) 422 { return actualTC->readFloatRegBits(reg_idx); } 423 424 CCReg readCCReg(int reg_idx) 425 { return actualTC->readCCReg(reg_idx); } 426 427 void setIntReg(int reg_idx, uint64_t val) 428 { actualTC->setIntReg(reg_idx, val); } 429 430 void setFloatReg(int reg_idx, FloatReg val) 431 { actualTC->setFloatReg(reg_idx, val); } 432 433 void setFloatRegBits(int reg_idx, FloatRegBits val) 434 { actualTC->setFloatRegBits(reg_idx, val); } 435 436 void setCCReg(int reg_idx, CCReg val) 437 { actualTC->setCCReg(reg_idx, val); } 438 439 TheISA::PCState pcState() { return actualTC->pcState(); } 440 441 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 442 443 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 444 445 Addr instAddr() { return actualTC->instAddr(); } 446 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 447 MicroPC microPC() { return actualTC->microPC(); } 448 449 bool readPredicate() { return actualTC->readPredicate(); } 450 451 void setPredicate(bool val) 452 { actualTC->setPredicate(val); } 453 454 MiscReg readMiscRegNoEffect(int misc_reg) const 455 { return actualTC->readMiscRegNoEffect(misc_reg); } 456 457 MiscReg readMiscReg(int misc_reg) 458 { return actualTC->readMiscReg(misc_reg); } 459 460 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 461 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 462 463 void setMiscReg(int misc_reg, const MiscReg &val) 464 { return actualTC->setMiscReg(misc_reg, val); } 465 466 RegId flattenRegId(const RegId& regId) const 467 { return actualTC->flattenRegId(regId); } 468 469 unsigned readStCondFailures() 470 { return actualTC->readStCondFailures(); } 471 472 void setStCondFailures(unsigned sc_failures) 473 { actualTC->setStCondFailures(sc_failures); } 474 475 void syscall(int64_t callnum, Fault *fault) 476 { actualTC->syscall(callnum, fault); } 477 478 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 479 480 uint64_t readIntRegFlat(int idx) 481 { return actualTC->readIntRegFlat(idx); } 482 483 void setIntRegFlat(int idx, uint64_t val) 484 { actualTC->setIntRegFlat(idx, val); } 485 486 FloatReg readFloatRegFlat(int idx) 487 { return actualTC->readFloatRegFlat(idx); } 488 489 void setFloatRegFlat(int idx, FloatReg val) 490 { actualTC->setFloatRegFlat(idx, val); } 491 492 FloatRegBits readFloatRegBitsFlat(int idx) 493 { return actualTC->readFloatRegBitsFlat(idx); } 494 495 void setFloatRegBitsFlat(int idx, FloatRegBits val) 496 { actualTC->setFloatRegBitsFlat(idx, val); } 497 498 CCReg readCCRegFlat(int idx) 499 { return actualTC->readCCRegFlat(idx); } 500 501 void setCCRegFlat(int idx, CCReg val) 502 { actualTC->setCCRegFlat(idx, val); } 503}; 504 505/** @{ */ 506/** 507 * Thread context serialization helpers 508 * 509 * These helper functions provide a way to the data in a 510 * ThreadContext. They are provided as separate helper function since 511 * implementing them as members of the ThreadContext interface would 512 * be confusing when the ThreadContext is exported via a proxy. 513 */ 514 515void serialize(ThreadContext &tc, CheckpointOut &cp); 516void unserialize(ThreadContext &tc, CheckpointIn &cp); 517 518/** @} */ 519 520 521/** 522 * Copy state between thread contexts in preparation for CPU handover. 523 * 524 * @note This method modifies the old thread contexts as well as the 525 * new thread context. The old thread context will have its quiesce 526 * event descheduled if it is scheduled and its status set to halted. 527 * 528 * @param new_tc Destination ThreadContext. 529 * @param old_tc Source ThreadContext. 530 */ 531void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 532 533#endif 534