thread_context.hh revision 10407:a9023811bf9e
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_THREAD_CONTEXT_HH__ 45#define __CPU_THREAD_CONTEXT_HH__ 46 47#include <iostream> 48#include <string> 49 50#include "arch/registers.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" 54 55// @todo: Figure out a more architecture independent way to obtain the ITB and 56// DTB pointers. 57namespace TheISA 58{ 59 class Decoder; 60 class TLB; 61} 62class BaseCPU; 63class CheckerCPU; 64class Checkpoint; 65class EndQuiesceEvent; 66class SETranslatingPortProxy; 67class FSTranslatingPortProxy; 68class PortProxy; 69class Process; 70class System; 71namespace TheISA { 72 namespace Kernel { 73 class Statistics; 74 } 75} 76 77/** 78 * ThreadContext is the external interface to all thread state for 79 * anything outside of the CPU. It provides all accessor methods to 80 * state that might be needed by external objects, ranging from 81 * register values to things such as kernel stats. It is an abstract 82 * base class; the CPU can create its own ThreadContext by either 83 * deriving from it, or using the templated ProxyThreadContext. 84 * 85 * The ThreadContext is slightly different than the ExecContext. The 86 * ThreadContext provides access to an individual thread's state; an 87 * ExecContext provides ISA access to the CPU (meaning it is 88 * implicitly multithreaded on SMT systems). Additionally the 89 * ThreadState is an abstract class that exactly defines the 90 * interface; the ExecContext is a more implicit interface that must 91 * be implemented so that the ISA can access whatever state it needs. 92 */ 93class ThreadContext 94{ 95 protected: 96 typedef TheISA::MachInst MachInst; 97 typedef TheISA::IntReg IntReg; 98 typedef TheISA::FloatReg FloatReg; 99 typedef TheISA::FloatRegBits FloatRegBits; 100 typedef TheISA::CCReg CCReg; 101 typedef TheISA::MiscReg MiscReg; 102 public: 103 104 enum Status 105 { 106 /// Running. Instructions should be executed only when 107 /// the context is in this state. 108 Active, 109 110 /// Temporarily inactive. Entered while waiting for 111 /// synchronization, etc. 112 Suspended, 113 114 /// Permanently shut down. Entered when target executes 115 /// m5exit pseudo-instruction. When all contexts enter 116 /// this state, the simulation will terminate. 117 Halted 118 }; 119 120 virtual ~ThreadContext() { }; 121 122 virtual BaseCPU *getCpuPtr() = 0; 123 124 virtual int cpuId() const = 0; 125 126 virtual uint32_t socketId() const = 0; 127 128 virtual int threadId() const = 0; 129 130 virtual void setThreadId(int id) = 0; 131 132 virtual int contextId() const = 0; 133 134 virtual void setContextId(int id) = 0; 135 136 virtual TheISA::TLB *getITBPtr() = 0; 137 138 virtual TheISA::TLB *getDTBPtr() = 0; 139 140 virtual CheckerCPU *getCheckerCpuPtr() = 0; 141 142 virtual TheISA::Decoder *getDecoderPtr() = 0; 143 144 virtual System *getSystemPtr() = 0; 145 146 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 147 148 virtual PortProxy &getPhysProxy() = 0; 149 150 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 151 152 /** 153 * Initialise the physical and virtual port proxies and tie them to 154 * the data port of the CPU. 155 * 156 * tc ThreadContext for the virtual-to-physical translation 157 */ 158 virtual void initMemProxies(ThreadContext *tc) = 0; 159 160 virtual SETranslatingPortProxy &getMemProxy() = 0; 161 162 virtual Process *getProcessPtr() = 0; 163 164 virtual Status status() const = 0; 165 166 virtual void setStatus(Status new_status) = 0; 167 168 /// Set the status to Active. 169 virtual void activate() = 0; 170 171 /// Set the status to Suspended. 172 virtual void suspend() = 0; 173 174 /// Set the status to Halted. 175 virtual void halt() = 0; 176 177 virtual void dumpFuncProfile() = 0; 178 179 virtual void takeOverFrom(ThreadContext *old_context) = 0; 180 181 virtual void regStats(const std::string &name) = 0; 182 183 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 184 185 // Not necessarily the best location for these... 186 // Having an extra function just to read these is obnoxious 187 virtual Tick readLastActivate() = 0; 188 virtual Tick readLastSuspend() = 0; 189 190 virtual void profileClear() = 0; 191 virtual void profileSample() = 0; 192 193 virtual void copyArchRegs(ThreadContext *tc) = 0; 194 195 virtual void clearArchRegs() = 0; 196 197 // 198 // New accessors for new decoder. 199 // 200 virtual uint64_t readIntReg(int reg_idx) = 0; 201 202 virtual FloatReg readFloatReg(int reg_idx) = 0; 203 204 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 205 206 virtual CCReg readCCReg(int reg_idx) = 0; 207 208 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 209 210 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 211 212 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 213 214 virtual void setCCReg(int reg_idx, CCReg val) = 0; 215 216 virtual TheISA::PCState pcState() = 0; 217 218 virtual void pcState(const TheISA::PCState &val) = 0; 219 220 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 221 222 virtual Addr instAddr() = 0; 223 224 virtual Addr nextInstAddr() = 0; 225 226 virtual MicroPC microPC() = 0; 227 228 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 229 230 virtual MiscReg readMiscReg(int misc_reg) = 0; 231 232 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 233 234 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 235 236 virtual int flattenIntIndex(int reg) = 0; 237 virtual int flattenFloatIndex(int reg) = 0; 238 virtual int flattenCCIndex(int reg) = 0; 239 virtual int flattenMiscIndex(int reg) = 0; 240 241 virtual uint64_t 242 readRegOtherThread(int misc_reg, ThreadID tid) 243 { 244 return 0; 245 } 246 247 virtual void 248 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 249 { 250 } 251 252 // Also not necessarily the best location for these two. Hopefully will go 253 // away once we decide upon where st cond failures goes. 254 virtual unsigned readStCondFailures() = 0; 255 256 virtual void setStCondFailures(unsigned sc_failures) = 0; 257 258 // Only really makes sense for old CPU model. Still could be useful though. 259 virtual bool misspeculating() = 0; 260 261 // Same with st cond failures. 262 virtual Counter readFuncExeInst() = 0; 263 264 virtual void syscall(int64_t callnum) = 0; 265 266 // This function exits the thread context in the CPU and returns 267 // 1 if the CPU has no more active threads (meaning it's OK to exit); 268 // Used in syscall-emulation mode when a thread calls the exit syscall. 269 virtual int exit() { return 1; }; 270 271 /** function to compare two thread contexts (for debugging) */ 272 static void compare(ThreadContext *one, ThreadContext *two); 273 274 /** @{ */ 275 /** 276 * Flat register interfaces 277 * 278 * Some architectures have different registers visible in 279 * different modes. Such architectures "flatten" a register (see 280 * flattenIntIndex() and flattenFloatIndex()) to map it into the 281 * gem5 register file. This interface provides a flat interface to 282 * the underlying register file, which allows for example 283 * serialization code to access all registers. 284 */ 285 286 virtual uint64_t readIntRegFlat(int idx) = 0; 287 virtual void setIntRegFlat(int idx, uint64_t val) = 0; 288 289 virtual FloatReg readFloatRegFlat(int idx) = 0; 290 virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 291 292 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 293 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 294 295 virtual CCReg readCCRegFlat(int idx) = 0; 296 virtual void setCCRegFlat(int idx, CCReg val) = 0; 297 /** @} */ 298 299}; 300 301/** 302 * ProxyThreadContext class that provides a way to implement a 303 * ThreadContext without having to derive from it. ThreadContext is an 304 * abstract class, so anything that derives from it and uses its 305 * interface will pay the overhead of virtual function calls. This 306 * class is created to enable a user-defined Thread object to be used 307 * wherever ThreadContexts are used, without paying the overhead of 308 * virtual function calls when it is used by itself. See 309 * simple_thread.hh for an example of this. 310 */ 311template <class TC> 312class ProxyThreadContext : public ThreadContext 313{ 314 public: 315 ProxyThreadContext(TC *actual_tc) 316 { actualTC = actual_tc; } 317 318 private: 319 TC *actualTC; 320 321 public: 322 323 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 324 325 int cpuId() const { return actualTC->cpuId(); } 326 327 uint32_t socketId() const { return actualTC->socketId(); } 328 329 int threadId() const { return actualTC->threadId(); } 330 331 void setThreadId(int id) { actualTC->setThreadId(id); } 332 333 int contextId() const { return actualTC->contextId(); } 334 335 void setContextId(int id) { actualTC->setContextId(id); } 336 337 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 338 339 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 340 341 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 342 343 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 344 345 System *getSystemPtr() { return actualTC->getSystemPtr(); } 346 347 TheISA::Kernel::Statistics *getKernelStats() 348 { return actualTC->getKernelStats(); } 349 350 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 351 352 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 353 354 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 355 356 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 357 358 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 359 360 Status status() const { return actualTC->status(); } 361 362 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 363 364 /// Set the status to Active. 365 void activate() { actualTC->activate(); } 366 367 /// Set the status to Suspended. 368 void suspend() { actualTC->suspend(); } 369 370 /// Set the status to Halted. 371 void halt() { actualTC->halt(); } 372 373 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 374 375 void takeOverFrom(ThreadContext *oldContext) 376 { actualTC->takeOverFrom(oldContext); } 377 378 void regStats(const std::string &name) { actualTC->regStats(name); } 379 380 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 381 382 Tick readLastActivate() { return actualTC->readLastActivate(); } 383 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 384 385 void profileClear() { return actualTC->profileClear(); } 386 void profileSample() { return actualTC->profileSample(); } 387 388 // @todo: Do I need this? 389 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 390 391 void clearArchRegs() { actualTC->clearArchRegs(); } 392 393 // 394 // New accessors for new decoder. 395 // 396 uint64_t readIntReg(int reg_idx) 397 { return actualTC->readIntReg(reg_idx); } 398 399 FloatReg readFloatReg(int reg_idx) 400 { return actualTC->readFloatReg(reg_idx); } 401 402 FloatRegBits readFloatRegBits(int reg_idx) 403 { return actualTC->readFloatRegBits(reg_idx); } 404 405 CCReg readCCReg(int reg_idx) 406 { return actualTC->readCCReg(reg_idx); } 407 408 void setIntReg(int reg_idx, uint64_t val) 409 { actualTC->setIntReg(reg_idx, val); } 410 411 void setFloatReg(int reg_idx, FloatReg val) 412 { actualTC->setFloatReg(reg_idx, val); } 413 414 void setFloatRegBits(int reg_idx, FloatRegBits val) 415 { actualTC->setFloatRegBits(reg_idx, val); } 416 417 void setCCReg(int reg_idx, CCReg val) 418 { actualTC->setCCReg(reg_idx, val); } 419 420 TheISA::PCState pcState() { return actualTC->pcState(); } 421 422 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 423 424 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 425 426 Addr instAddr() { return actualTC->instAddr(); } 427 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 428 MicroPC microPC() { return actualTC->microPC(); } 429 430 bool readPredicate() { return actualTC->readPredicate(); } 431 432 void setPredicate(bool val) 433 { actualTC->setPredicate(val); } 434 435 MiscReg readMiscRegNoEffect(int misc_reg) 436 { return actualTC->readMiscRegNoEffect(misc_reg); } 437 438 MiscReg readMiscReg(int misc_reg) 439 { return actualTC->readMiscReg(misc_reg); } 440 441 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 442 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 443 444 void setMiscReg(int misc_reg, const MiscReg &val) 445 { return actualTC->setMiscReg(misc_reg, val); } 446 447 int flattenIntIndex(int reg) 448 { return actualTC->flattenIntIndex(reg); } 449 450 int flattenFloatIndex(int reg) 451 { return actualTC->flattenFloatIndex(reg); } 452 453 int flattenCCIndex(int reg) 454 { return actualTC->flattenCCIndex(reg); } 455 456 int flattenMiscIndex(int reg) 457 { return actualTC->flattenMiscIndex(reg); } 458 459 unsigned readStCondFailures() 460 { return actualTC->readStCondFailures(); } 461 462 void setStCondFailures(unsigned sc_failures) 463 { actualTC->setStCondFailures(sc_failures); } 464 465 // @todo: Fix this! 466 bool misspeculating() { return actualTC->misspeculating(); } 467 468 void syscall(int64_t callnum) 469 { actualTC->syscall(callnum); } 470 471 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 472 473 uint64_t readIntRegFlat(int idx) 474 { return actualTC->readIntRegFlat(idx); } 475 476 void setIntRegFlat(int idx, uint64_t val) 477 { actualTC->setIntRegFlat(idx, val); } 478 479 FloatReg readFloatRegFlat(int idx) 480 { return actualTC->readFloatRegFlat(idx); } 481 482 void setFloatRegFlat(int idx, FloatReg val) 483 { actualTC->setFloatRegFlat(idx, val); } 484 485 FloatRegBits readFloatRegBitsFlat(int idx) 486 { return actualTC->readFloatRegBitsFlat(idx); } 487 488 void setFloatRegBitsFlat(int idx, FloatRegBits val) 489 { actualTC->setFloatRegBitsFlat(idx, val); } 490 491 CCReg readCCRegFlat(int idx) 492 { return actualTC->readCCRegFlat(idx); } 493 494 void setCCRegFlat(int idx, CCReg val) 495 { actualTC->setCCRegFlat(idx, val); } 496}; 497 498/** @{ */ 499/** 500 * Thread context serialization helpers 501 * 502 * These helper functions provide a way to the data in a 503 * ThreadContext. They are provided as separate helper function since 504 * implementing them as members of the ThreadContext interface would 505 * be confusing when the ThreadContext is exported via a proxy. 506 */ 507 508void serialize(ThreadContext &tc, std::ostream &os); 509void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 510 511/** @} */ 512 513 514/** 515 * Copy state between thread contexts in preparation for CPU handover. 516 * 517 * @note This method modifies the old thread contexts as well as the 518 * new thread context. The old thread context will have its quiesce 519 * event descheduled if it is scheduled and its status set to halted. 520 * 521 * @param new_tc Destination ThreadContext. 522 * @param old_tc Source ThreadContext. 523 */ 524void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 525 526#endif 527