thread_context.hh revision 10190
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_THREAD_CONTEXT_HH__ 45#define __CPU_THREAD_CONTEXT_HH__ 46 47#include <iostream> 48#include <string> 49 50#include "arch/registers.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/the_isa.hh" 54 55// @todo: Figure out a more architecture independent way to obtain the ITB and 56// DTB pointers. 57namespace TheISA 58{ 59 class Decoder; 60 class TLB; 61} 62class BaseCPU; 63class CheckerCPU; 64class Checkpoint; 65class EndQuiesceEvent; 66class SETranslatingPortProxy; 67class FSTranslatingPortProxy; 68class PortProxy; 69class Process; 70class System; 71namespace TheISA { 72 namespace Kernel { 73 class Statistics; 74 } 75} 76 77/** 78 * ThreadContext is the external interface to all thread state for 79 * anything outside of the CPU. It provides all accessor methods to 80 * state that might be needed by external objects, ranging from 81 * register values to things such as kernel stats. It is an abstract 82 * base class; the CPU can create its own ThreadContext by either 83 * deriving from it, or using the templated ProxyThreadContext. 84 * 85 * The ThreadContext is slightly different than the ExecContext. The 86 * ThreadContext provides access to an individual thread's state; an 87 * ExecContext provides ISA access to the CPU (meaning it is 88 * implicitly multithreaded on SMT systems). Additionally the 89 * ThreadState is an abstract class that exactly defines the 90 * interface; the ExecContext is a more implicit interface that must 91 * be implemented so that the ISA can access whatever state it needs. 92 */ 93class ThreadContext 94{ 95 protected: 96 typedef TheISA::MachInst MachInst; 97 typedef TheISA::IntReg IntReg; 98 typedef TheISA::FloatReg FloatReg; 99 typedef TheISA::FloatRegBits FloatRegBits; 100 typedef TheISA::CCReg CCReg; 101 typedef TheISA::MiscReg MiscReg; 102 public: 103 104 enum Status 105 { 106 /// Running. Instructions should be executed only when 107 /// the context is in this state. 108 Active, 109 110 /// Temporarily inactive. Entered while waiting for 111 /// synchronization, etc. 112 Suspended, 113 114 /// Permanently shut down. Entered when target executes 115 /// m5exit pseudo-instruction. When all contexts enter 116 /// this state, the simulation will terminate. 117 Halted 118 }; 119 120 virtual ~ThreadContext() { }; 121 122 virtual BaseCPU *getCpuPtr() = 0; 123 124 virtual int cpuId() const = 0; 125 126 virtual uint32_t socketId() const = 0; 127 128 virtual int threadId() const = 0; 129 130 virtual void setThreadId(int id) = 0; 131 132 virtual int contextId() const = 0; 133 134 virtual void setContextId(int id) = 0; 135 136 virtual TheISA::TLB *getITBPtr() = 0; 137 138 virtual TheISA::TLB *getDTBPtr() = 0; 139 140 virtual CheckerCPU *getCheckerCpuPtr() = 0; 141 142 virtual TheISA::Decoder *getDecoderPtr() = 0; 143 144 virtual System *getSystemPtr() = 0; 145 146 virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 147 148 virtual PortProxy &getPhysProxy() = 0; 149 150 virtual FSTranslatingPortProxy &getVirtProxy() = 0; 151 152 /** 153 * Initialise the physical and virtual port proxies and tie them to 154 * the data port of the CPU. 155 * 156 * tc ThreadContext for the virtual-to-physical translation 157 */ 158 virtual void initMemProxies(ThreadContext *tc) = 0; 159 160 virtual SETranslatingPortProxy &getMemProxy() = 0; 161 162 virtual Process *getProcessPtr() = 0; 163 164 virtual Status status() const = 0; 165 166 virtual void setStatus(Status new_status) = 0; 167 168 /// Set the status to Active. Optional delay indicates number of 169 /// cycles to wait before beginning execution. 170 virtual void activate(Cycles delay = Cycles(1)) = 0; 171 172 /// Set the status to Suspended. 173 virtual void suspend(Cycles delay = Cycles(0)) = 0; 174 175 /// Set the status to Halted. 176 virtual void halt(Cycles delay = Cycles(0)) = 0; 177 178 virtual void dumpFuncProfile() = 0; 179 180 virtual void takeOverFrom(ThreadContext *old_context) = 0; 181 182 virtual void regStats(const std::string &name) = 0; 183 184 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 185 186 // Not necessarily the best location for these... 187 // Having an extra function just to read these is obnoxious 188 virtual Tick readLastActivate() = 0; 189 virtual Tick readLastSuspend() = 0; 190 191 virtual void profileClear() = 0; 192 virtual void profileSample() = 0; 193 194 virtual void copyArchRegs(ThreadContext *tc) = 0; 195 196 virtual void clearArchRegs() = 0; 197 198 // 199 // New accessors for new decoder. 200 // 201 virtual uint64_t readIntReg(int reg_idx) = 0; 202 203 virtual FloatReg readFloatReg(int reg_idx) = 0; 204 205 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 206 207 virtual CCReg readCCReg(int reg_idx) = 0; 208 209 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 210 211 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 212 213 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 214 215 virtual void setCCReg(int reg_idx, CCReg val) = 0; 216 217 virtual TheISA::PCState pcState() = 0; 218 219 virtual void pcState(const TheISA::PCState &val) = 0; 220 221 virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 222 223 virtual Addr instAddr() = 0; 224 225 virtual Addr nextInstAddr() = 0; 226 227 virtual MicroPC microPC() = 0; 228 229 virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 230 231 virtual MiscReg readMiscReg(int misc_reg) = 0; 232 233 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 234 235 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 236 237 virtual int flattenIntIndex(int reg) = 0; 238 virtual int flattenFloatIndex(int reg) = 0; 239 virtual int flattenCCIndex(int reg) = 0; 240 virtual int flattenMiscIndex(int reg) = 0; 241 242 virtual uint64_t 243 readRegOtherThread(int misc_reg, ThreadID tid) 244 { 245 return 0; 246 } 247 248 virtual void 249 setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 250 { 251 } 252 253 // Also not necessarily the best location for these two. Hopefully will go 254 // away once we decide upon where st cond failures goes. 255 virtual unsigned readStCondFailures() = 0; 256 257 virtual void setStCondFailures(unsigned sc_failures) = 0; 258 259 // Only really makes sense for old CPU model. Still could be useful though. 260 virtual bool misspeculating() = 0; 261 262 // Same with st cond failures. 263 virtual Counter readFuncExeInst() = 0; 264 265 virtual void syscall(int64_t callnum) = 0; 266 267 // This function exits the thread context in the CPU and returns 268 // 1 if the CPU has no more active threads (meaning it's OK to exit); 269 // Used in syscall-emulation mode when a thread calls the exit syscall. 270 virtual int exit() { return 1; }; 271 272 /** function to compare two thread contexts (for debugging) */ 273 static void compare(ThreadContext *one, ThreadContext *two); 274 275 /** @{ */ 276 /** 277 * Flat register interfaces 278 * 279 * Some architectures have different registers visible in 280 * different modes. Such architectures "flatten" a register (see 281 * flattenIntIndex() and flattenFloatIndex()) to map it into the 282 * gem5 register file. This interface provides a flat interface to 283 * the underlying register file, which allows for example 284 * serialization code to access all registers. 285 */ 286 287 virtual uint64_t readIntRegFlat(int idx) = 0; 288 virtual void setIntRegFlat(int idx, uint64_t val) = 0; 289 290 virtual FloatReg readFloatRegFlat(int idx) = 0; 291 virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 292 293 virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 294 virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 295 296 virtual CCReg readCCRegFlat(int idx) = 0; 297 virtual void setCCRegFlat(int idx, CCReg val) = 0; 298 /** @} */ 299 300}; 301 302/** 303 * ProxyThreadContext class that provides a way to implement a 304 * ThreadContext without having to derive from it. ThreadContext is an 305 * abstract class, so anything that derives from it and uses its 306 * interface will pay the overhead of virtual function calls. This 307 * class is created to enable a user-defined Thread object to be used 308 * wherever ThreadContexts are used, without paying the overhead of 309 * virtual function calls when it is used by itself. See 310 * simple_thread.hh for an example of this. 311 */ 312template <class TC> 313class ProxyThreadContext : public ThreadContext 314{ 315 public: 316 ProxyThreadContext(TC *actual_tc) 317 { actualTC = actual_tc; } 318 319 private: 320 TC *actualTC; 321 322 public: 323 324 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 325 326 int cpuId() const { return actualTC->cpuId(); } 327 328 uint32_t socketId() const { return actualTC->socketId(); } 329 330 int threadId() const { return actualTC->threadId(); } 331 332 void setThreadId(int id) { actualTC->setThreadId(id); } 333 334 int contextId() const { return actualTC->contextId(); } 335 336 void setContextId(int id) { actualTC->setContextId(id); } 337 338 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 339 340 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 341 342 CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 343 344 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 345 346 System *getSystemPtr() { return actualTC->getSystemPtr(); } 347 348 TheISA::Kernel::Statistics *getKernelStats() 349 { return actualTC->getKernelStats(); } 350 351 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 352 353 FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 354 355 void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 356 357 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 358 359 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 360 361 Status status() const { return actualTC->status(); } 362 363 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 364 365 /// Set the status to Active. Optional delay indicates number of 366 /// cycles to wait before beginning execution. 367 void activate(Cycles delay = Cycles(1)) 368 { actualTC->activate(delay); } 369 370 /// Set the status to Suspended. 371 void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 372 373 /// Set the status to Halted. 374 void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 375 376 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 377 378 void takeOverFrom(ThreadContext *oldContext) 379 { actualTC->takeOverFrom(oldContext); } 380 381 void regStats(const std::string &name) { actualTC->regStats(name); } 382 383 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 384 385 Tick readLastActivate() { return actualTC->readLastActivate(); } 386 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 387 388 void profileClear() { return actualTC->profileClear(); } 389 void profileSample() { return actualTC->profileSample(); } 390 391 // @todo: Do I need this? 392 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 393 394 void clearArchRegs() { actualTC->clearArchRegs(); } 395 396 // 397 // New accessors for new decoder. 398 // 399 uint64_t readIntReg(int reg_idx) 400 { return actualTC->readIntReg(reg_idx); } 401 402 FloatReg readFloatReg(int reg_idx) 403 { return actualTC->readFloatReg(reg_idx); } 404 405 FloatRegBits readFloatRegBits(int reg_idx) 406 { return actualTC->readFloatRegBits(reg_idx); } 407 408 CCReg readCCReg(int reg_idx) 409 { return actualTC->readCCReg(reg_idx); } 410 411 void setIntReg(int reg_idx, uint64_t val) 412 { actualTC->setIntReg(reg_idx, val); } 413 414 void setFloatReg(int reg_idx, FloatReg val) 415 { actualTC->setFloatReg(reg_idx, val); } 416 417 void setFloatRegBits(int reg_idx, FloatRegBits val) 418 { actualTC->setFloatRegBits(reg_idx, val); } 419 420 void setCCReg(int reg_idx, CCReg val) 421 { actualTC->setCCReg(reg_idx, val); } 422 423 TheISA::PCState pcState() { return actualTC->pcState(); } 424 425 void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 426 427 void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 428 429 Addr instAddr() { return actualTC->instAddr(); } 430 Addr nextInstAddr() { return actualTC->nextInstAddr(); } 431 MicroPC microPC() { return actualTC->microPC(); } 432 433 bool readPredicate() { return actualTC->readPredicate(); } 434 435 void setPredicate(bool val) 436 { actualTC->setPredicate(val); } 437 438 MiscReg readMiscRegNoEffect(int misc_reg) 439 { return actualTC->readMiscRegNoEffect(misc_reg); } 440 441 MiscReg readMiscReg(int misc_reg) 442 { return actualTC->readMiscReg(misc_reg); } 443 444 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 445 { return actualTC->setMiscRegNoEffect(misc_reg, val); } 446 447 void setMiscReg(int misc_reg, const MiscReg &val) 448 { return actualTC->setMiscReg(misc_reg, val); } 449 450 int flattenIntIndex(int reg) 451 { return actualTC->flattenIntIndex(reg); } 452 453 int flattenFloatIndex(int reg) 454 { return actualTC->flattenFloatIndex(reg); } 455 456 int flattenCCIndex(int reg) 457 { return actualTC->flattenCCIndex(reg); } 458 459 int flattenMiscIndex(int reg) 460 { return actualTC->flattenMiscIndex(reg); } 461 462 unsigned readStCondFailures() 463 { return actualTC->readStCondFailures(); } 464 465 void setStCondFailures(unsigned sc_failures) 466 { actualTC->setStCondFailures(sc_failures); } 467 468 // @todo: Fix this! 469 bool misspeculating() { return actualTC->misspeculating(); } 470 471 void syscall(int64_t callnum) 472 { actualTC->syscall(callnum); } 473 474 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 475 476 uint64_t readIntRegFlat(int idx) 477 { return actualTC->readIntRegFlat(idx); } 478 479 void setIntRegFlat(int idx, uint64_t val) 480 { actualTC->setIntRegFlat(idx, val); } 481 482 FloatReg readFloatRegFlat(int idx) 483 { return actualTC->readFloatRegFlat(idx); } 484 485 void setFloatRegFlat(int idx, FloatReg val) 486 { actualTC->setFloatRegFlat(idx, val); } 487 488 FloatRegBits readFloatRegBitsFlat(int idx) 489 { return actualTC->readFloatRegBitsFlat(idx); } 490 491 void setFloatRegBitsFlat(int idx, FloatRegBits val) 492 { actualTC->setFloatRegBitsFlat(idx, val); } 493 494 CCReg readCCRegFlat(int idx) 495 { return actualTC->readCCRegFlat(idx); } 496 497 void setCCRegFlat(int idx, CCReg val) 498 { actualTC->setCCRegFlat(idx, val); } 499}; 500 501/** @{ */ 502/** 503 * Thread context serialization helpers 504 * 505 * These helper functions provide a way to the data in a 506 * ThreadContext. They are provided as separate helper function since 507 * implementing them as members of the ThreadContext interface would 508 * be confusing when the ThreadContext is exported via a proxy. 509 */ 510 511void serialize(ThreadContext &tc, std::ostream &os); 512void unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 513 514/** @} */ 515 516 517/** 518 * Copy state between thread contexts in preparation for CPU handover. 519 * 520 * @note This method modifies the old thread contexts as well as the 521 * new thread context. The old thread context will have its quiesce 522 * event descheduled if it is scheduled and its status set to halted. 523 * 524 * @param new_tc Destination ThreadContext. 525 * @param old_tc Source ThreadContext. 526 */ 527void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 528 529#endif 530