thread_context.hh revision 9920
12SN/A/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 542SN/A 552190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 562190SN/A// DTB pointers. 573453Sgblack@eecs.umich.edunamespace TheISA 583453Sgblack@eecs.umich.edu{ 599020Sgblack@eecs.umich.edu class Decoder; 606022Sgblack@eecs.umich.edu class TLB; 613453Sgblack@eecs.umich.edu} 622190SN/Aclass BaseCPU; 638887Sgeoffrey.blake@arm.comclass CheckerCPU; 647680Sgblack@eecs.umich.educlass Checkpoint; 652313SN/Aclass EndQuiesceEvent; 668706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 678706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 688706Sandreas.hansson@arm.comclass PortProxy; 692190SN/Aclass Process; 702190SN/Aclass System; 713548Sgblack@eecs.umich.edunamespace TheISA { 723548Sgblack@eecs.umich.edu namespace Kernel { 733548Sgblack@eecs.umich.edu class Statistics; 748902Sandreas.hansson@arm.com } 758902Sandreas.hansson@arm.com} 762SN/A 772680Sktlim@umich.edu/** 782680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 792680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 802680Sktlim@umich.edu * state that might be needed by external objects, ranging from 812680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 822680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 832680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 842680Sktlim@umich.edu * 852680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 862680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 872680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 882682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 892680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 902680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 912680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 922680Sktlim@umich.edu */ 932680Sktlim@umich.educlass ThreadContext 942SN/A{ 952107SN/A protected: 962107SN/A typedef TheISA::MachInst MachInst; 972190SN/A typedef TheISA::IntReg IntReg; 982455SN/A typedef TheISA::FloatReg FloatReg; 992455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1009920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 1012159SN/A typedef TheISA::MiscReg MiscReg; 1022SN/A public: 1036029Ssteve.reinhardt@amd.com 104246SN/A enum Status 105246SN/A { 106246SN/A /// Running. Instructions should be executed only when 107246SN/A /// the context is in this state. 108246SN/A Active, 109246SN/A 110246SN/A /// Temporarily inactive. Entered while waiting for 1112190SN/A /// synchronization, etc. 112246SN/A Suspended, 113246SN/A 114246SN/A /// Permanently shut down. Entered when target executes 115246SN/A /// m5exit pseudo-instruction. When all contexts enter 116246SN/A /// this state, the simulation will terminate. 117246SN/A Halted 118246SN/A }; 1192SN/A 1202680Sktlim@umich.edu virtual ~ThreadContext() { }; 1212423SN/A 1222190SN/A virtual BaseCPU *getCpuPtr() = 0; 123180SN/A 1245712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1252190SN/A 1265715Shsul@eecs.umich.edu virtual int threadId() = 0; 1275715Shsul@eecs.umich.edu 1285715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1295714Shsul@eecs.umich.edu 1305714Shsul@eecs.umich.edu virtual int contextId() = 0; 1315714Shsul@eecs.umich.edu 1325714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1335714Shsul@eecs.umich.edu 1346022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1352190SN/A 1366022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1372521SN/A 1388887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1398733Sgeoffrey.blake@arm.com 1409020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1418541Sgblack@eecs.umich.edu 1424997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1434997Sgblack@eecs.umich.edu 1443548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1452654SN/A 1468852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1472521SN/A 1488852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1493673Srdreslin@umich.edu 1508706Sandreas.hansson@arm.com /** 1518706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1528706Sandreas.hansson@arm.com * the data port of the CPU. 1538706Sandreas.hansson@arm.com * 1548706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1558706Sandreas.hansson@arm.com */ 1568706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1578799Sgblack@eecs.umich.edu 1588852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1592518SN/A 1602190SN/A virtual Process *getProcessPtr() = 0; 1612190SN/A 1622190SN/A virtual Status status() const = 0; 1632159SN/A 1642235SN/A virtual void setStatus(Status new_status) = 0; 1652103SN/A 166393SN/A /// Set the status to Active. Optional delay indicates number of 167393SN/A /// cycles to wait before beginning execution. 1689180Sandreas.hansson@arm.com virtual void activate(Cycles delay = Cycles(1)) = 0; 169393SN/A 170393SN/A /// Set the status to Suspended. 1719180Sandreas.hansson@arm.com virtual void suspend(Cycles delay = Cycles(0)) = 0; 172393SN/A 173393SN/A /// Set the status to Halted. 1749180Sandreas.hansson@arm.com virtual void halt(Cycles delay = Cycles(0)) = 0; 1752159SN/A 1762190SN/A virtual void dumpFuncProfile() = 0; 1772159SN/A 1782680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1792159SN/A 1802190SN/A virtual void regStats(const std::string &name) = 0; 1812159SN/A 1822313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1832235SN/A 1842235SN/A // Not necessarily the best location for these... 1852235SN/A // Having an extra function just to read these is obnoxious 1862235SN/A virtual Tick readLastActivate() = 0; 1872235SN/A virtual Tick readLastSuspend() = 0; 1882254SN/A 1892254SN/A virtual void profileClear() = 0; 1902254SN/A virtual void profileSample() = 0; 1912235SN/A 1922680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1932159SN/A 1942190SN/A virtual void clearArchRegs() = 0; 1952159SN/A 1962159SN/A // 1972159SN/A // New accessors for new decoder. 1982159SN/A // 1992190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2002159SN/A 2012455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2022159SN/A 2032455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2042159SN/A 2059920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) = 0; 2069920Syasuko.eckert@amd.com 2072190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2082159SN/A 2092455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2102159SN/A 2112455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2122455SN/A 2139920Syasuko.eckert@amd.com virtual void setCCReg(int reg_idx, CCReg val) = 0; 2149920Syasuko.eckert@amd.com 2157720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2162159SN/A 2177720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2182159SN/A 2198733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2208733Sgeoffrey.blake@arm.com 2217720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2222159SN/A 2237720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2242159SN/A 2257720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2265260Sksewell@umich.edu 2274172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2284172Ssaidi@eecs.umich.edu 2292190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2302159SN/A 2314172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2322190SN/A 2333468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2342190SN/A 2356313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2366313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2379920Syasuko.eckert@amd.com virtual int flattenCCIndex(int reg) = 0; 2386313Sgblack@eecs.umich.edu 2396221Snate@binkert.org virtual uint64_t 2406221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2416221Snate@binkert.org { 2426221Snate@binkert.org return 0; 2436221Snate@binkert.org } 2444661Sksewell@umich.edu 2456221Snate@binkert.org virtual void 2466221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2476221Snate@binkert.org { 2486221Snate@binkert.org } 2494661Sksewell@umich.edu 2502235SN/A // Also not necessarily the best location for these two. Hopefully will go 2512235SN/A // away once we decide upon where st cond failures goes. 2522190SN/A virtual unsigned readStCondFailures() = 0; 2532190SN/A 2542190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2552159SN/A 2562235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2572190SN/A virtual bool misspeculating() = 0; 2582190SN/A 2592235SN/A // Same with st cond failures. 2602190SN/A virtual Counter readFuncExeInst() = 0; 2612834Sksewell@umich.edu 2624111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2634111Sgblack@eecs.umich.edu 2642834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2652834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2662834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2672834Sksewell@umich.edu virtual int exit() { return 1; }; 2682525SN/A 2695217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2705217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2719426SAndreas.Sandberg@ARM.com 2729426SAndreas.Sandberg@ARM.com /** @{ */ 2739426SAndreas.Sandberg@ARM.com /** 2749426SAndreas.Sandberg@ARM.com * Flat register interfaces 2759426SAndreas.Sandberg@ARM.com * 2769426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 2779426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 2789426SAndreas.Sandberg@ARM.com * flattenIntIndex() and flattenFloatIndex()) to map it into the 2799426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 2809426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 2819426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 2829426SAndreas.Sandberg@ARM.com */ 2839426SAndreas.Sandberg@ARM.com 2849426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx) = 0; 2859426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val) = 0; 2869426SAndreas.Sandberg@ARM.com 2879426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx) = 0; 2889426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 2899426SAndreas.Sandberg@ARM.com 2909426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 2919426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 2929426SAndreas.Sandberg@ARM.com 2939920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx) = 0; 2949920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val) = 0; 2959426SAndreas.Sandberg@ARM.com /** @} */ 2969426SAndreas.Sandberg@ARM.com 2972159SN/A}; 2982159SN/A 2992682Sktlim@umich.edu/** 3002682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 3012682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 3022682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 3032682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 3042682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 3052682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3062682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3072682Sktlim@umich.edu * simple_thread.hh for an example of this. 3082682Sktlim@umich.edu */ 3092680Sktlim@umich.edutemplate <class TC> 3102680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3112190SN/A{ 3122190SN/A public: 3132680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3142680Sktlim@umich.edu { actualTC = actual_tc; } 3152159SN/A 3162190SN/A private: 3172680Sktlim@umich.edu TC *actualTC; 3182SN/A 3192SN/A public: 3202SN/A 3212680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3222SN/A 3235712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 3242SN/A 3255715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 3265715Shsul@eecs.umich.edu 3275715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 3285714Shsul@eecs.umich.edu 3295714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 3305714Shsul@eecs.umich.edu 3315714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3325714Shsul@eecs.umich.edu 3336022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3341917SN/A 3356022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3362521SN/A 3378887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3388733Sgeoffrey.blake@arm.com 3399020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3408541Sgblack@eecs.umich.edu 3414997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3424997Sgblack@eecs.umich.edu 3433548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3443548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3452654SN/A 3468852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 3472521SN/A 3488852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 3493673Srdreslin@umich.edu 3508706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3518799Sgblack@eecs.umich.edu 3528852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 3532518SN/A 3542680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3552SN/A 3562680Sktlim@umich.edu Status status() const { return actualTC->status(); } 357595SN/A 3582680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3592SN/A 3602190SN/A /// Set the status to Active. Optional delay indicates number of 3612190SN/A /// cycles to wait before beginning execution. 3629180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)) 3639180Sandreas.hansson@arm.com { actualTC->activate(delay); } 3642SN/A 3652190SN/A /// Set the status to Suspended. 3669180Sandreas.hansson@arm.com void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 3672SN/A 3682190SN/A /// Set the status to Halted. 3699180Sandreas.hansson@arm.com void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 370217SN/A 3712680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3722190SN/A 3732680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3742680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3752190SN/A 3762680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3772190SN/A 3782680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3792235SN/A 3802680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3812680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3822254SN/A 3832680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3842680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3852SN/A 3862190SN/A // @todo: Do I need this? 3872680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3882SN/A 3892680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 390716SN/A 3912SN/A // 3922SN/A // New accessors for new decoder. 3932SN/A // 3942SN/A uint64_t readIntReg(int reg_idx) 3952680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3962SN/A 3972455SN/A FloatReg readFloatReg(int reg_idx) 3982680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3992SN/A 4002455SN/A FloatRegBits readFloatRegBits(int reg_idx) 4012680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4022SN/A 4039920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 4049920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 4059920Syasuko.eckert@amd.com 4062SN/A void setIntReg(int reg_idx, uint64_t val) 4072680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 4082SN/A 4092455SN/A void setFloatReg(int reg_idx, FloatReg val) 4102680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4112SN/A 4122455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4132680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4142SN/A 4159920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 4169920Syasuko.eckert@amd.com { actualTC->setCCReg(reg_idx, val); } 4179920Syasuko.eckert@amd.com 4187720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 4192SN/A 4207720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 4212206SN/A 4228733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 4238733Sgeoffrey.blake@arm.com 4247720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4257720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 4267720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 4275260Sksewell@umich.edu 4287597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 4297597Sminkyu.jeong@arm.com 4307597Sminkyu.jeong@arm.com void setPredicate(bool val) 4317597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 4327597Sminkyu.jeong@arm.com 4334172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4344172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4354172Ssaidi@eecs.umich.edu 4362159SN/A MiscReg readMiscReg(int misc_reg) 4372680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4382SN/A 4394172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4404172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4412SN/A 4423468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4432680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4442SN/A 4456313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4466313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4476313Sgblack@eecs.umich.edu 4486313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4496313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4506313Sgblack@eecs.umich.edu 4519920Syasuko.eckert@amd.com int flattenCCIndex(int reg) 4529920Syasuko.eckert@amd.com { return actualTC->flattenCCIndex(reg); } 4539920Syasuko.eckert@amd.com 4542190SN/A unsigned readStCondFailures() 4552680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4562190SN/A 4572190SN/A void setStCondFailures(unsigned sc_failures) 4582680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4592SN/A 4602190SN/A // @todo: Fix this! 4612680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4622190SN/A 4634111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4644111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4654111Sgblack@eecs.umich.edu 4662680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4679426SAndreas.Sandberg@ARM.com 4689426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 4699426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 4709426SAndreas.Sandberg@ARM.com 4719426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 4729426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 4739426SAndreas.Sandberg@ARM.com 4749426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 4759426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 4769426SAndreas.Sandberg@ARM.com 4779426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 4789426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 4799426SAndreas.Sandberg@ARM.com 4809426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 4819426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 4829426SAndreas.Sandberg@ARM.com 4839426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 4849426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 4859920Syasuko.eckert@amd.com 4869920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 4879920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 4889920Syasuko.eckert@amd.com 4899920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 4909920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 4912SN/A}; 4922SN/A 4939428SAndreas.Sandberg@ARM.com/** @{ */ 4949428SAndreas.Sandberg@ARM.com/** 4959428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 4969428SAndreas.Sandberg@ARM.com * 4979428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 4989428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 4999428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 5009428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 5019428SAndreas.Sandberg@ARM.com */ 5029428SAndreas.Sandberg@ARM.com 5039428SAndreas.Sandberg@ARM.comvoid serialize(ThreadContext &tc, std::ostream &os); 5049428SAndreas.Sandberg@ARM.comvoid unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 5059428SAndreas.Sandberg@ARM.com 5069428SAndreas.Sandberg@ARM.com/** @} */ 5079428SAndreas.Sandberg@ARM.com 5089441SAndreas.Sandberg@ARM.com 5099441SAndreas.Sandberg@ARM.com/** 5109441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 5119441SAndreas.Sandberg@ARM.com * 5129441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 5139441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 5149441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 5159441SAndreas.Sandberg@ARM.com * 5169441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 5179441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 5189441SAndreas.Sandberg@ARM.com */ 5199441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 5209441SAndreas.Sandberg@ARM.com 5212190SN/A#endif 522