thread_context.hh revision 9426
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 412SN/A */ 422SN/A 432680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 442680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 452SN/A 468229Snate@binkert.org#include <iostream> 477680Sgblack@eecs.umich.edu#include <string> 487680Sgblack@eecs.umich.edu 496329Sgblack@eecs.umich.edu#include "arch/registers.hh" 503453Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 532SN/A 542190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 552190SN/A// DTB pointers. 563453Sgblack@eecs.umich.edunamespace TheISA 573453Sgblack@eecs.umich.edu{ 589020Sgblack@eecs.umich.edu class Decoder; 596022Sgblack@eecs.umich.edu class TLB; 603453Sgblack@eecs.umich.edu} 612190SN/Aclass BaseCPU; 628887Sgeoffrey.blake@arm.comclass CheckerCPU; 637680Sgblack@eecs.umich.educlass Checkpoint; 642313SN/Aclass EndQuiesceEvent; 658706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 668706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 678706Sandreas.hansson@arm.comclass PortProxy; 682190SN/Aclass Process; 692190SN/Aclass System; 703548Sgblack@eecs.umich.edunamespace TheISA { 713548Sgblack@eecs.umich.edu namespace Kernel { 723548Sgblack@eecs.umich.edu class Statistics; 738902Sandreas.hansson@arm.com } 748902Sandreas.hansson@arm.com} 752SN/A 762680Sktlim@umich.edu/** 772680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 782680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 792680Sktlim@umich.edu * state that might be needed by external objects, ranging from 802680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 812680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 822680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 832680Sktlim@umich.edu * 842680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 852680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 862680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 872682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 882680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 892680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 902680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 912680Sktlim@umich.edu */ 922680Sktlim@umich.educlass ThreadContext 932SN/A{ 942107SN/A protected: 952107SN/A typedef TheISA::MachInst MachInst; 962190SN/A typedef TheISA::IntReg IntReg; 972455SN/A typedef TheISA::FloatReg FloatReg; 982455SN/A typedef TheISA::FloatRegBits FloatRegBits; 992159SN/A typedef TheISA::MiscReg MiscReg; 1002SN/A public: 1016029Ssteve.reinhardt@amd.com 102246SN/A enum Status 103246SN/A { 104246SN/A /// Running. Instructions should be executed only when 105246SN/A /// the context is in this state. 106246SN/A Active, 107246SN/A 108246SN/A /// Temporarily inactive. Entered while waiting for 1092190SN/A /// synchronization, etc. 110246SN/A Suspended, 111246SN/A 112246SN/A /// Permanently shut down. Entered when target executes 113246SN/A /// m5exit pseudo-instruction. When all contexts enter 114246SN/A /// this state, the simulation will terminate. 115246SN/A Halted 116246SN/A }; 1172SN/A 1182680Sktlim@umich.edu virtual ~ThreadContext() { }; 1192423SN/A 1202190SN/A virtual BaseCPU *getCpuPtr() = 0; 121180SN/A 1225712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1232190SN/A 1245715Shsul@eecs.umich.edu virtual int threadId() = 0; 1255715Shsul@eecs.umich.edu 1265715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1275714Shsul@eecs.umich.edu 1285714Shsul@eecs.umich.edu virtual int contextId() = 0; 1295714Shsul@eecs.umich.edu 1305714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1315714Shsul@eecs.umich.edu 1326022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1332190SN/A 1346022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1352521SN/A 1368887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1378733Sgeoffrey.blake@arm.com 1389020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1398541Sgblack@eecs.umich.edu 1404997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1414997Sgblack@eecs.umich.edu 1423548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1432654SN/A 1448852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1452521SN/A 1468852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1473673Srdreslin@umich.edu 1488706Sandreas.hansson@arm.com /** 1498706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1508706Sandreas.hansson@arm.com * the data port of the CPU. 1518706Sandreas.hansson@arm.com * 1528706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1538706Sandreas.hansson@arm.com */ 1548706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1558799Sgblack@eecs.umich.edu 1568852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1572518SN/A 1582190SN/A virtual Process *getProcessPtr() = 0; 1592190SN/A 1602190SN/A virtual Status status() const = 0; 1612159SN/A 1622235SN/A virtual void setStatus(Status new_status) = 0; 1632103SN/A 164393SN/A /// Set the status to Active. Optional delay indicates number of 165393SN/A /// cycles to wait before beginning execution. 1669180Sandreas.hansson@arm.com virtual void activate(Cycles delay = Cycles(1)) = 0; 167393SN/A 168393SN/A /// Set the status to Suspended. 1699180Sandreas.hansson@arm.com virtual void suspend(Cycles delay = Cycles(0)) = 0; 170393SN/A 171393SN/A /// Set the status to Halted. 1729180Sandreas.hansson@arm.com virtual void halt(Cycles delay = Cycles(0)) = 0; 1732159SN/A 1742190SN/A virtual void dumpFuncProfile() = 0; 1752159SN/A 1762680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1772159SN/A 1782190SN/A virtual void regStats(const std::string &name) = 0; 1792159SN/A 1802190SN/A virtual void serialize(std::ostream &os) = 0; 1812190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1822159SN/A 1832313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1842235SN/A 1852235SN/A // Not necessarily the best location for these... 1862235SN/A // Having an extra function just to read these is obnoxious 1872235SN/A virtual Tick readLastActivate() = 0; 1882235SN/A virtual Tick readLastSuspend() = 0; 1892254SN/A 1902254SN/A virtual void profileClear() = 0; 1912254SN/A virtual void profileSample() = 0; 1922235SN/A 1932680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1942159SN/A 1952190SN/A virtual void clearArchRegs() = 0; 1962159SN/A 1972159SN/A // 1982159SN/A // New accessors for new decoder. 1992159SN/A // 2002190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2012159SN/A 2022455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2032159SN/A 2042455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2052159SN/A 2062190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2072159SN/A 2082455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2092159SN/A 2102455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2112455SN/A 2127720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2132159SN/A 2147720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2152159SN/A 2168733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2178733Sgeoffrey.blake@arm.com 2187720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2192159SN/A 2207720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2212159SN/A 2227720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2235260Sksewell@umich.edu 2244172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2254172Ssaidi@eecs.umich.edu 2262190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2272159SN/A 2284172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2292190SN/A 2303468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2312190SN/A 2326313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2336313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2346313Sgblack@eecs.umich.edu 2356221Snate@binkert.org virtual uint64_t 2366221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2376221Snate@binkert.org { 2386221Snate@binkert.org return 0; 2396221Snate@binkert.org } 2404661Sksewell@umich.edu 2416221Snate@binkert.org virtual void 2426221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2436221Snate@binkert.org { 2446221Snate@binkert.org } 2454661Sksewell@umich.edu 2462235SN/A // Also not necessarily the best location for these two. Hopefully will go 2472235SN/A // away once we decide upon where st cond failures goes. 2482190SN/A virtual unsigned readStCondFailures() = 0; 2492190SN/A 2502190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2512159SN/A 2522235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2532190SN/A virtual bool misspeculating() = 0; 2542190SN/A 2552235SN/A // Same with st cond failures. 2562190SN/A virtual Counter readFuncExeInst() = 0; 2572834Sksewell@umich.edu 2584111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2594111Sgblack@eecs.umich.edu 2602834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2612834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2622834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2632834Sksewell@umich.edu virtual int exit() { return 1; }; 2642525SN/A 2655217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2665217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2679426SAndreas.Sandberg@ARM.com 2689426SAndreas.Sandberg@ARM.com /** @{ */ 2699426SAndreas.Sandberg@ARM.com /** 2709426SAndreas.Sandberg@ARM.com * Flat register interfaces 2719426SAndreas.Sandberg@ARM.com * 2729426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 2739426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 2749426SAndreas.Sandberg@ARM.com * flattenIntIndex() and flattenFloatIndex()) to map it into the 2759426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 2769426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 2779426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 2789426SAndreas.Sandberg@ARM.com */ 2799426SAndreas.Sandberg@ARM.com 2809426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx) = 0; 2819426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val) = 0; 2829426SAndreas.Sandberg@ARM.com 2839426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx) = 0; 2849426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 2859426SAndreas.Sandberg@ARM.com 2869426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 2879426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 2889426SAndreas.Sandberg@ARM.com 2899426SAndreas.Sandberg@ARM.com /** @} */ 2909426SAndreas.Sandberg@ARM.com 2912159SN/A}; 2922159SN/A 2932682Sktlim@umich.edu/** 2942682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2952682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2962682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2972682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2982682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2992682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3002682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3012682Sktlim@umich.edu * simple_thread.hh for an example of this. 3022682Sktlim@umich.edu */ 3032680Sktlim@umich.edutemplate <class TC> 3042680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3052190SN/A{ 3062190SN/A public: 3072680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3082680Sktlim@umich.edu { actualTC = actual_tc; } 3092159SN/A 3102190SN/A private: 3112680Sktlim@umich.edu TC *actualTC; 3122SN/A 3132SN/A public: 3142SN/A 3152680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3162SN/A 3175712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 3182SN/A 3195715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 3205715Shsul@eecs.umich.edu 3215715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 3225714Shsul@eecs.umich.edu 3235714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 3245714Shsul@eecs.umich.edu 3255714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3265714Shsul@eecs.umich.edu 3276022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3281917SN/A 3296022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3302521SN/A 3318887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3328733Sgeoffrey.blake@arm.com 3339020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3348541Sgblack@eecs.umich.edu 3354997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3364997Sgblack@eecs.umich.edu 3373548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3383548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3392654SN/A 3408852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 3412521SN/A 3428852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 3433673Srdreslin@umich.edu 3448706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3458799Sgblack@eecs.umich.edu 3468852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 3472518SN/A 3482680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3492SN/A 3502680Sktlim@umich.edu Status status() const { return actualTC->status(); } 351595SN/A 3522680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3532SN/A 3542190SN/A /// Set the status to Active. Optional delay indicates number of 3552190SN/A /// cycles to wait before beginning execution. 3569180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)) 3579180Sandreas.hansson@arm.com { actualTC->activate(delay); } 3582SN/A 3592190SN/A /// Set the status to Suspended. 3609180Sandreas.hansson@arm.com void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 3612SN/A 3622190SN/A /// Set the status to Halted. 3639180Sandreas.hansson@arm.com void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 364217SN/A 3652680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3662190SN/A 3672680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3682680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3692190SN/A 3702680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3712190SN/A 3722680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3732190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3742680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3752190SN/A 3762680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3772235SN/A 3782680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3792680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3802254SN/A 3812680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3822680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3832SN/A 3842190SN/A // @todo: Do I need this? 3852680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3862SN/A 3872680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 388716SN/A 3892SN/A // 3902SN/A // New accessors for new decoder. 3912SN/A // 3922SN/A uint64_t readIntReg(int reg_idx) 3932680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3942SN/A 3952455SN/A FloatReg readFloatReg(int reg_idx) 3962680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3972SN/A 3982455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3992680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4002SN/A 4012SN/A void setIntReg(int reg_idx, uint64_t val) 4022680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 4032SN/A 4042455SN/A void setFloatReg(int reg_idx, FloatReg val) 4052680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4062SN/A 4072455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4082680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4092SN/A 4107720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 4112SN/A 4127720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 4132206SN/A 4148733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 4158733Sgeoffrey.blake@arm.com 4167720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4177720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 4187720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 4195260Sksewell@umich.edu 4207597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 4217597Sminkyu.jeong@arm.com 4227597Sminkyu.jeong@arm.com void setPredicate(bool val) 4237597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 4247597Sminkyu.jeong@arm.com 4254172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4264172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4274172Ssaidi@eecs.umich.edu 4282159SN/A MiscReg readMiscReg(int misc_reg) 4292680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4302SN/A 4314172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4324172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4332SN/A 4343468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4352680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4362SN/A 4376313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4386313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4396313Sgblack@eecs.umich.edu 4406313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4416313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4426313Sgblack@eecs.umich.edu 4432190SN/A unsigned readStCondFailures() 4442680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4452190SN/A 4462190SN/A void setStCondFailures(unsigned sc_failures) 4472680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4482SN/A 4492190SN/A // @todo: Fix this! 4502680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4512190SN/A 4524111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4534111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4544111Sgblack@eecs.umich.edu 4552680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4569426SAndreas.Sandberg@ARM.com 4579426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 4589426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 4599426SAndreas.Sandberg@ARM.com 4609426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 4619426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 4629426SAndreas.Sandberg@ARM.com 4639426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 4649426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 4659426SAndreas.Sandberg@ARM.com 4669426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 4679426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 4689426SAndreas.Sandberg@ARM.com 4699426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 4709426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 4719426SAndreas.Sandberg@ARM.com 4729426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 4739426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 4742SN/A}; 4752SN/A 4762190SN/A#endif 477