thread_context.hh revision 8852
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 412SN/A */ 422SN/A 432680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 442680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 452SN/A 468229Snate@binkert.org#include <iostream> 477680Sgblack@eecs.umich.edu#include <string> 487680Sgblack@eecs.umich.edu 496329Sgblack@eecs.umich.edu#include "arch/registers.hh" 503453Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 538733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 542SN/A 552190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 562190SN/A// DTB pointers. 573453Sgblack@eecs.umich.edunamespace TheISA 583453Sgblack@eecs.umich.edu{ 596022Sgblack@eecs.umich.edu class TLB; 603453Sgblack@eecs.umich.edu} 612190SN/Aclass BaseCPU; 627680Sgblack@eecs.umich.educlass Checkpoint; 638541Sgblack@eecs.umich.educlass Decoder; 642313SN/Aclass EndQuiesceEvent; 658706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 668706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 678706Sandreas.hansson@arm.comclass PortProxy; 682190SN/Aclass Process; 692190SN/Aclass System; 703548Sgblack@eecs.umich.edunamespace TheISA { 713548Sgblack@eecs.umich.edu namespace Kernel { 723548Sgblack@eecs.umich.edu class Statistics; 733548Sgblack@eecs.umich.edu }; 742330SN/A}; 752SN/A 762680Sktlim@umich.edu/** 772680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 782680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 792680Sktlim@umich.edu * state that might be needed by external objects, ranging from 802680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 812680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 822680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 832680Sktlim@umich.edu * 842680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 852680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 862680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 872682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 882680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 892680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 902680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 912680Sktlim@umich.edu */ 922680Sktlim@umich.educlass ThreadContext 932SN/A{ 942107SN/A protected: 952107SN/A typedef TheISA::MachInst MachInst; 962190SN/A typedef TheISA::IntReg IntReg; 972455SN/A typedef TheISA::FloatReg FloatReg; 982455SN/A typedef TheISA::FloatRegBits FloatRegBits; 992159SN/A typedef TheISA::MiscReg MiscReg; 1002SN/A public: 1016029Ssteve.reinhardt@amd.com 102246SN/A enum Status 103246SN/A { 104246SN/A /// Running. Instructions should be executed only when 105246SN/A /// the context is in this state. 106246SN/A Active, 107246SN/A 108246SN/A /// Temporarily inactive. Entered while waiting for 1092190SN/A /// synchronization, etc. 110246SN/A Suspended, 111246SN/A 112246SN/A /// Permanently shut down. Entered when target executes 113246SN/A /// m5exit pseudo-instruction. When all contexts enter 114246SN/A /// this state, the simulation will terminate. 115246SN/A Halted 116246SN/A }; 1172SN/A 1182680Sktlim@umich.edu virtual ~ThreadContext() { }; 1192423SN/A 1202190SN/A virtual BaseCPU *getCpuPtr() = 0; 121180SN/A 1225712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1232190SN/A 1245715Shsul@eecs.umich.edu virtual int threadId() = 0; 1255715Shsul@eecs.umich.edu 1265715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1275714Shsul@eecs.umich.edu 1285714Shsul@eecs.umich.edu virtual int contextId() = 0; 1295714Shsul@eecs.umich.edu 1305714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1315714Shsul@eecs.umich.edu 1326022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1332190SN/A 1346022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1352521SN/A 1368733Sgeoffrey.blake@arm.com#if USE_CHECKER 1378733Sgeoffrey.blake@arm.com virtual BaseCPU *getCheckerCpuPtr() = 0; 1388733Sgeoffrey.blake@arm.com#endif 1398733Sgeoffrey.blake@arm.com 1408541Sgblack@eecs.umich.edu virtual Decoder *getDecoderPtr() = 0; 1418541Sgblack@eecs.umich.edu 1424997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1434997Sgblack@eecs.umich.edu 1443548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1452654SN/A 1468852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1472521SN/A 1488852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1493673Srdreslin@umich.edu 1508706Sandreas.hansson@arm.com /** 1518706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1528706Sandreas.hansson@arm.com * the data port of the CPU. 1538706Sandreas.hansson@arm.com * 1548706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1558706Sandreas.hansson@arm.com */ 1568706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1578799Sgblack@eecs.umich.edu 1588852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1592518SN/A 1602190SN/A virtual Process *getProcessPtr() = 0; 1612190SN/A 1622190SN/A virtual Status status() const = 0; 1632159SN/A 1642235SN/A virtual void setStatus(Status new_status) = 0; 1652103SN/A 166393SN/A /// Set the status to Active. Optional delay indicates number of 167393SN/A /// cycles to wait before beginning execution. 1682190SN/A virtual void activate(int delay = 1) = 0; 169393SN/A 170393SN/A /// Set the status to Suspended. 1715250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 172393SN/A 173393SN/A /// Set the status to Halted. 1745250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1752159SN/A 1762190SN/A virtual void dumpFuncProfile() = 0; 1772159SN/A 1782680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1792159SN/A 1802190SN/A virtual void regStats(const std::string &name) = 0; 1812159SN/A 1822190SN/A virtual void serialize(std::ostream &os) = 0; 1832190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1842159SN/A 1852313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1862235SN/A 1872235SN/A // Not necessarily the best location for these... 1882235SN/A // Having an extra function just to read these is obnoxious 1892235SN/A virtual Tick readLastActivate() = 0; 1902235SN/A virtual Tick readLastSuspend() = 0; 1912254SN/A 1922254SN/A virtual void profileClear() = 0; 1932254SN/A virtual void profileSample() = 0; 1942235SN/A 1952680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1962159SN/A 1972190SN/A virtual void clearArchRegs() = 0; 1982159SN/A 1992159SN/A // 2002159SN/A // New accessors for new decoder. 2012159SN/A // 2022190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2032159SN/A 2042455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2052159SN/A 2062455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2072159SN/A 2082190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2092159SN/A 2102455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2112159SN/A 2122455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2132455SN/A 2147720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2152159SN/A 2167720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2172159SN/A 2188733Sgeoffrey.blake@arm.com#if USE_CHECKER 2198733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2208733Sgeoffrey.blake@arm.com#endif 2218733Sgeoffrey.blake@arm.com 2227720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2232159SN/A 2247720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2252159SN/A 2267720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2275260Sksewell@umich.edu 2284172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2294172Ssaidi@eecs.umich.edu 2302190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2312159SN/A 2324172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2332190SN/A 2343468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2352190SN/A 2366313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2376313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2386313Sgblack@eecs.umich.edu 2396221Snate@binkert.org virtual uint64_t 2406221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2416221Snate@binkert.org { 2426221Snate@binkert.org return 0; 2436221Snate@binkert.org } 2444661Sksewell@umich.edu 2456221Snate@binkert.org virtual void 2466221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2476221Snate@binkert.org { 2486221Snate@binkert.org } 2494661Sksewell@umich.edu 2502235SN/A // Also not necessarily the best location for these two. Hopefully will go 2512235SN/A // away once we decide upon where st cond failures goes. 2522190SN/A virtual unsigned readStCondFailures() = 0; 2532190SN/A 2542190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2552159SN/A 2562235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2572190SN/A virtual bool misspeculating() = 0; 2582190SN/A 2592235SN/A // Same with st cond failures. 2602190SN/A virtual Counter readFuncExeInst() = 0; 2612834Sksewell@umich.edu 2624111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2634111Sgblack@eecs.umich.edu 2642834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2652834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2662834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2672834Sksewell@umich.edu virtual int exit() { return 1; }; 2682525SN/A 2695217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2705217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2712159SN/A}; 2722159SN/A 2732682Sktlim@umich.edu/** 2742682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2752682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2762682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2772682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2782682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2792682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2802682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2812682Sktlim@umich.edu * simple_thread.hh for an example of this. 2822682Sktlim@umich.edu */ 2832680Sktlim@umich.edutemplate <class TC> 2842680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2852190SN/A{ 2862190SN/A public: 2872680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2882680Sktlim@umich.edu { actualTC = actual_tc; } 2892159SN/A 2902190SN/A private: 2912680Sktlim@umich.edu TC *actualTC; 2922SN/A 2932SN/A public: 2942SN/A 2952680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2962SN/A 2975712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2982SN/A 2995715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 3005715Shsul@eecs.umich.edu 3015715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 3025714Shsul@eecs.umich.edu 3035714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 3045714Shsul@eecs.umich.edu 3055714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3065714Shsul@eecs.umich.edu 3076022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3081917SN/A 3096022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3102521SN/A 3118733Sgeoffrey.blake@arm.com#if USE_CHECKER 3128733Sgeoffrey.blake@arm.com BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3138733Sgeoffrey.blake@arm.com#endif 3148733Sgeoffrey.blake@arm.com 3158541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3168541Sgblack@eecs.umich.edu 3174997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3184997Sgblack@eecs.umich.edu 3193548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3203548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3212654SN/A 3228852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 3232521SN/A 3248852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 3253673Srdreslin@umich.edu 3268706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3278799Sgblack@eecs.umich.edu 3288852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 3292518SN/A 3302680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3312SN/A 3322680Sktlim@umich.edu Status status() const { return actualTC->status(); } 333595SN/A 3342680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3352SN/A 3362190SN/A /// Set the status to Active. Optional delay indicates number of 3372190SN/A /// cycles to wait before beginning execution. 3382680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3392SN/A 3402190SN/A /// Set the status to Suspended. 3415250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3422SN/A 3432190SN/A /// Set the status to Halted. 3445250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 345217SN/A 3462680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3472190SN/A 3482680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3492680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3502190SN/A 3512680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3522190SN/A 3532680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3542190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3552680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3562190SN/A 3572680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3582235SN/A 3592680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3602680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3612254SN/A 3622680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3632680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3642SN/A 3652190SN/A // @todo: Do I need this? 3662680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3672SN/A 3682680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 369716SN/A 3702SN/A // 3712SN/A // New accessors for new decoder. 3722SN/A // 3732SN/A uint64_t readIntReg(int reg_idx) 3742680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3752SN/A 3762455SN/A FloatReg readFloatReg(int reg_idx) 3772680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3782SN/A 3792455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3802680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3812SN/A 3822SN/A void setIntReg(int reg_idx, uint64_t val) 3832680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3842SN/A 3852455SN/A void setFloatReg(int reg_idx, FloatReg val) 3862680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3872SN/A 3882455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3892680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3902SN/A 3917720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 3922SN/A 3937720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 3942206SN/A 3958733Sgeoffrey.blake@arm.com#if USE_CHECKER 3968733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 3978733Sgeoffrey.blake@arm.com#endif 3988733Sgeoffrey.blake@arm.com 3997720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4007720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 4017720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 4025260Sksewell@umich.edu 4037597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 4047597Sminkyu.jeong@arm.com 4057597Sminkyu.jeong@arm.com void setPredicate(bool val) 4067597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 4077597Sminkyu.jeong@arm.com 4084172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4094172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4104172Ssaidi@eecs.umich.edu 4112159SN/A MiscReg readMiscReg(int misc_reg) 4122680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4132SN/A 4144172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4154172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4162SN/A 4173468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4182680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4192SN/A 4206313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4216313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4226313Sgblack@eecs.umich.edu 4236313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4246313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4256313Sgblack@eecs.umich.edu 4262190SN/A unsigned readStCondFailures() 4272680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4282190SN/A 4292190SN/A void setStCondFailures(unsigned sc_failures) 4302680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4312SN/A 4322190SN/A // @todo: Fix this! 4332680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4342190SN/A 4354111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4364111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4374111Sgblack@eecs.umich.edu 4382680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4392SN/A}; 4402SN/A 4412190SN/A#endif 442