thread_context.hh revision 8706
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 348229Snate@binkert.org#include <iostream> 357680Sgblack@eecs.umich.edu#include <string> 367680Sgblack@eecs.umich.edu 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 383453Sgblack@eecs.umich.edu#include "arch/types.hh" 396216Snate@binkert.org#include "base/types.hh" 401858SN/A#include "config/full_system.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 422SN/A 432190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 442190SN/A// DTB pointers. 453453Sgblack@eecs.umich.edunamespace TheISA 463453Sgblack@eecs.umich.edu{ 476022Sgblack@eecs.umich.edu class TLB; 483453Sgblack@eecs.umich.edu} 492190SN/Aclass BaseCPU; 507680Sgblack@eecs.umich.educlass Checkpoint; 518541Sgblack@eecs.umich.educlass Decoder; 522313SN/Aclass EndQuiesceEvent; 538706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 548706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 558706Sandreas.hansson@arm.comclass PortProxy; 562190SN/Aclass Process; 572190SN/Aclass System; 583548Sgblack@eecs.umich.edunamespace TheISA { 593548Sgblack@eecs.umich.edu namespace Kernel { 603548Sgblack@eecs.umich.edu class Statistics; 613548Sgblack@eecs.umich.edu }; 622330SN/A}; 632SN/A 642680Sktlim@umich.edu/** 652680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 662680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 672680Sktlim@umich.edu * state that might be needed by external objects, ranging from 682680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 692680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 702680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 712680Sktlim@umich.edu * 722680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 732680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 742680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 752682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 762680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 772680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 782680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 792680Sktlim@umich.edu */ 802680Sktlim@umich.educlass ThreadContext 812SN/A{ 822107SN/A protected: 832107SN/A typedef TheISA::MachInst MachInst; 842190SN/A typedef TheISA::IntReg IntReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872159SN/A typedef TheISA::MiscReg MiscReg; 882SN/A public: 896029Ssteve.reinhardt@amd.com 90246SN/A enum Status 91246SN/A { 92246SN/A /// Running. Instructions should be executed only when 93246SN/A /// the context is in this state. 94246SN/A Active, 95246SN/A 96246SN/A /// Temporarily inactive. Entered while waiting for 972190SN/A /// synchronization, etc. 98246SN/A Suspended, 99246SN/A 100246SN/A /// Permanently shut down. Entered when target executes 101246SN/A /// m5exit pseudo-instruction. When all contexts enter 102246SN/A /// this state, the simulation will terminate. 103246SN/A Halted 104246SN/A }; 1052SN/A 1062680Sktlim@umich.edu virtual ~ThreadContext() { }; 1072423SN/A 1082190SN/A virtual BaseCPU *getCpuPtr() = 0; 109180SN/A 1105712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1112190SN/A 1125715Shsul@eecs.umich.edu virtual int threadId() = 0; 1135715Shsul@eecs.umich.edu 1145715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1155714Shsul@eecs.umich.edu 1165714Shsul@eecs.umich.edu virtual int contextId() = 0; 1175714Shsul@eecs.umich.edu 1185714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1195714Shsul@eecs.umich.edu 1206022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1212190SN/A 1226022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1232521SN/A 1248541Sgblack@eecs.umich.edu virtual Decoder *getDecoderPtr() = 0; 1258541Sgblack@eecs.umich.edu 1264997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1274997Sgblack@eecs.umich.edu 1285803Snate@binkert.org#if FULL_SYSTEM 1293548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1302654SN/A 1318706Sandreas.hansson@arm.com virtual PortProxy* getPhysProxy() = 0; 1322521SN/A 1338706Sandreas.hansson@arm.com virtual FSTranslatingPortProxy* getVirtProxy() = 0; 1343673Srdreslin@umich.edu 1358706Sandreas.hansson@arm.com /** 1368706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1378706Sandreas.hansson@arm.com * the data port of the CPU. 1388706Sandreas.hansson@arm.com * 1398706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1408706Sandreas.hansson@arm.com */ 1418706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1422190SN/A#else 1438706Sandreas.hansson@arm.com virtual SETranslatingPortProxy *getMemProxy() = 0; 1442518SN/A 1452190SN/A virtual Process *getProcessPtr() = 0; 1462190SN/A#endif 1472190SN/A 1482190SN/A virtual Status status() const = 0; 1492159SN/A 1502235SN/A virtual void setStatus(Status new_status) = 0; 1512103SN/A 152393SN/A /// Set the status to Active. Optional delay indicates number of 153393SN/A /// cycles to wait before beginning execution. 1542190SN/A virtual void activate(int delay = 1) = 0; 155393SN/A 156393SN/A /// Set the status to Suspended. 1575250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 158393SN/A 159393SN/A /// Set the status to Halted. 1605250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1612159SN/A 1622159SN/A#if FULL_SYSTEM 1632190SN/A virtual void dumpFuncProfile() = 0; 1642159SN/A#endif 1652159SN/A 1662680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1672159SN/A 1682190SN/A virtual void regStats(const std::string &name) = 0; 1692159SN/A 1702190SN/A virtual void serialize(std::ostream &os) = 0; 1712190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1722159SN/A 1732235SN/A#if FULL_SYSTEM 1742313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1752235SN/A 1762235SN/A // Not necessarily the best location for these... 1772235SN/A // Having an extra function just to read these is obnoxious 1782235SN/A virtual Tick readLastActivate() = 0; 1792235SN/A virtual Tick readLastSuspend() = 0; 1802254SN/A 1812254SN/A virtual void profileClear() = 0; 1822254SN/A virtual void profileSample() = 0; 1832235SN/A#endif 1842235SN/A 1852680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1862159SN/A 1872190SN/A virtual void clearArchRegs() = 0; 1882159SN/A 1892159SN/A // 1902159SN/A // New accessors for new decoder. 1912159SN/A // 1922190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1932159SN/A 1942455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1952159SN/A 1962455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1972159SN/A 1982190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 1992159SN/A 2002455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2012159SN/A 2022455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2032455SN/A 2047720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2052159SN/A 2067720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2072159SN/A 2087720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2092159SN/A 2107720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2112159SN/A 2127720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2135260Sksewell@umich.edu 2144172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2154172Ssaidi@eecs.umich.edu 2162190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2172159SN/A 2184172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2192190SN/A 2203468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2212190SN/A 2226313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2236313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2246313Sgblack@eecs.umich.edu 2256221Snate@binkert.org virtual uint64_t 2266221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2276221Snate@binkert.org { 2286221Snate@binkert.org return 0; 2296221Snate@binkert.org } 2304661Sksewell@umich.edu 2316221Snate@binkert.org virtual void 2326221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2336221Snate@binkert.org { 2346221Snate@binkert.org } 2354661Sksewell@umich.edu 2362235SN/A // Also not necessarily the best location for these two. Hopefully will go 2372235SN/A // away once we decide upon where st cond failures goes. 2382190SN/A virtual unsigned readStCondFailures() = 0; 2392190SN/A 2402190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2412159SN/A 2422235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2432190SN/A virtual bool misspeculating() = 0; 2442190SN/A 2452159SN/A#if !FULL_SYSTEM 2462235SN/A // Same with st cond failures. 2472190SN/A virtual Counter readFuncExeInst() = 0; 2482834Sksewell@umich.edu 2494111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2504111Sgblack@eecs.umich.edu 2512834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2522834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2532834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2542834Sksewell@umich.edu virtual int exit() { return 1; }; 2552159SN/A#endif 2562525SN/A 2575217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2585217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2592159SN/A}; 2602159SN/A 2612682Sktlim@umich.edu/** 2622682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2632682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2642682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2652682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2662682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2672682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2682682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2692682Sktlim@umich.edu * simple_thread.hh for an example of this. 2702682Sktlim@umich.edu */ 2712680Sktlim@umich.edutemplate <class TC> 2722680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2732190SN/A{ 2742190SN/A public: 2752680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2762680Sktlim@umich.edu { actualTC = actual_tc; } 2772159SN/A 2782190SN/A private: 2792680Sktlim@umich.edu TC *actualTC; 2802SN/A 2812SN/A public: 2822SN/A 2832680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2842SN/A 2855712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2862SN/A 2875715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 2885715Shsul@eecs.umich.edu 2895715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 2905714Shsul@eecs.umich.edu 2915714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 2925714Shsul@eecs.umich.edu 2935714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 2945714Shsul@eecs.umich.edu 2956022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 2961917SN/A 2976022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 2982521SN/A 2998541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3008541Sgblack@eecs.umich.edu 3014997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3024997Sgblack@eecs.umich.edu 3035803Snate@binkert.org#if FULL_SYSTEM 3043548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3053548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3062654SN/A 3078706Sandreas.hansson@arm.com PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 3082521SN/A 3098706Sandreas.hansson@arm.com FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } 3103673Srdreslin@umich.edu 3118706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3122SN/A#else 3138706Sandreas.hansson@arm.com SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } 3142518SN/A 3152680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3162SN/A#endif 3172SN/A 3182680Sktlim@umich.edu Status status() const { return actualTC->status(); } 319595SN/A 3202680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3212SN/A 3222190SN/A /// Set the status to Active. Optional delay indicates number of 3232190SN/A /// cycles to wait before beginning execution. 3242680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3252SN/A 3262190SN/A /// Set the status to Suspended. 3275250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3282SN/A 3292190SN/A /// Set the status to Halted. 3305250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 331217SN/A 3321858SN/A#if FULL_SYSTEM 3332680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3342190SN/A#endif 3352190SN/A 3362680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3372680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3382190SN/A 3392680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3402190SN/A 3412680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3422190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3432680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3442190SN/A 3452235SN/A#if FULL_SYSTEM 3462680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3472235SN/A 3482680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3492680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3502254SN/A 3512680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3522680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3532235SN/A#endif 3542SN/A 3552190SN/A // @todo: Do I need this? 3562680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3572SN/A 3582680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 359716SN/A 3602SN/A // 3612SN/A // New accessors for new decoder. 3622SN/A // 3632SN/A uint64_t readIntReg(int reg_idx) 3642680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3652SN/A 3662455SN/A FloatReg readFloatReg(int reg_idx) 3672680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3682SN/A 3692455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3702680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3712SN/A 3722SN/A void setIntReg(int reg_idx, uint64_t val) 3732680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3742SN/A 3752455SN/A void setFloatReg(int reg_idx, FloatReg val) 3762680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3772SN/A 3782455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3792680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3802SN/A 3817720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 3822SN/A 3837720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 3842206SN/A 3857720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 3867720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 3877720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 3885260Sksewell@umich.edu 3897597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 3907597Sminkyu.jeong@arm.com 3917597Sminkyu.jeong@arm.com void setPredicate(bool val) 3927597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 3937597Sminkyu.jeong@arm.com 3944172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3954172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 3964172Ssaidi@eecs.umich.edu 3972159SN/A MiscReg readMiscReg(int misc_reg) 3982680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 3992SN/A 4004172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4014172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4022SN/A 4033468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4042680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4052SN/A 4066313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4076313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4086313Sgblack@eecs.umich.edu 4096313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4106313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4116313Sgblack@eecs.umich.edu 4122190SN/A unsigned readStCondFailures() 4132680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4142190SN/A 4152190SN/A void setStCondFailures(unsigned sc_failures) 4162680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4172SN/A 4182190SN/A // @todo: Fix this! 4192680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4202190SN/A 4211858SN/A#if !FULL_SYSTEM 4224111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4234111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4244111Sgblack@eecs.umich.edu 4252680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4262SN/A#endif 4272SN/A}; 4282SN/A 4292190SN/A#endif 430