thread_context.hh revision 8541
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 348229Snate@binkert.org#include <iostream> 357680Sgblack@eecs.umich.edu#include <string> 367680Sgblack@eecs.umich.edu 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 383453Sgblack@eecs.umich.edu#include "arch/types.hh" 396216Snate@binkert.org#include "base/types.hh" 401858SN/A#include "config/full_system.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 422SN/A 432190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 442190SN/A// DTB pointers. 453453Sgblack@eecs.umich.edunamespace TheISA 463453Sgblack@eecs.umich.edu{ 476022Sgblack@eecs.umich.edu class TLB; 483453Sgblack@eecs.umich.edu} 492190SN/Aclass BaseCPU; 507680Sgblack@eecs.umich.educlass Checkpoint; 518541Sgblack@eecs.umich.educlass Decoder; 522313SN/Aclass EndQuiesceEvent; 532423SN/Aclass TranslatingPort; 542521SN/Aclass FunctionalPort; 552521SN/Aclass VirtualPort; 562190SN/Aclass Process; 572190SN/Aclass System; 583548Sgblack@eecs.umich.edunamespace TheISA { 593548Sgblack@eecs.umich.edu namespace Kernel { 603548Sgblack@eecs.umich.edu class Statistics; 613548Sgblack@eecs.umich.edu }; 622330SN/A}; 632SN/A 642680Sktlim@umich.edu/** 652680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 662680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 672680Sktlim@umich.edu * state that might be needed by external objects, ranging from 682680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 692680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 702680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 712680Sktlim@umich.edu * 722680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 732680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 742680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 752682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 762680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 772680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 782680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 792680Sktlim@umich.edu */ 802680Sktlim@umich.educlass ThreadContext 812SN/A{ 822107SN/A protected: 832107SN/A typedef TheISA::MachInst MachInst; 842190SN/A typedef TheISA::IntReg IntReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872159SN/A typedef TheISA::MiscReg MiscReg; 882SN/A public: 896029Ssteve.reinhardt@amd.com 90246SN/A enum Status 91246SN/A { 92246SN/A /// Running. Instructions should be executed only when 93246SN/A /// the context is in this state. 94246SN/A Active, 95246SN/A 96246SN/A /// Temporarily inactive. Entered while waiting for 972190SN/A /// synchronization, etc. 98246SN/A Suspended, 99246SN/A 100246SN/A /// Permanently shut down. Entered when target executes 101246SN/A /// m5exit pseudo-instruction. When all contexts enter 102246SN/A /// this state, the simulation will terminate. 103246SN/A Halted 104246SN/A }; 1052SN/A 1062680Sktlim@umich.edu virtual ~ThreadContext() { }; 1072423SN/A 1082190SN/A virtual BaseCPU *getCpuPtr() = 0; 109180SN/A 1105712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1112190SN/A 1125715Shsul@eecs.umich.edu virtual int threadId() = 0; 1135715Shsul@eecs.umich.edu 1145715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1155714Shsul@eecs.umich.edu 1165714Shsul@eecs.umich.edu virtual int contextId() = 0; 1175714Shsul@eecs.umich.edu 1185714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1195714Shsul@eecs.umich.edu 1206022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1212190SN/A 1226022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1232521SN/A 1248541Sgblack@eecs.umich.edu virtual Decoder *getDecoderPtr() = 0; 1258541Sgblack@eecs.umich.edu 1264997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1274997Sgblack@eecs.umich.edu 1285803Snate@binkert.org#if FULL_SYSTEM 1293548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1302654SN/A 1312521SN/A virtual FunctionalPort *getPhysPort() = 0; 1322521SN/A 1335499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort() = 0; 1343673Srdreslin@umich.edu 1355497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) = 0; 1362190SN/A#else 1372518SN/A virtual TranslatingPort *getMemPort() = 0; 1382518SN/A 1392190SN/A virtual Process *getProcessPtr() = 0; 1402190SN/A#endif 1412190SN/A 1422190SN/A virtual Status status() const = 0; 1432159SN/A 1442235SN/A virtual void setStatus(Status new_status) = 0; 1452103SN/A 146393SN/A /// Set the status to Active. Optional delay indicates number of 147393SN/A /// cycles to wait before beginning execution. 1482190SN/A virtual void activate(int delay = 1) = 0; 149393SN/A 150393SN/A /// Set the status to Suspended. 1515250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 152393SN/A 153393SN/A /// Set the status to Halted. 1545250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1552159SN/A 1562159SN/A#if FULL_SYSTEM 1572190SN/A virtual void dumpFuncProfile() = 0; 1582159SN/A#endif 1592159SN/A 1602680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1612159SN/A 1622190SN/A virtual void regStats(const std::string &name) = 0; 1632159SN/A 1642190SN/A virtual void serialize(std::ostream &os) = 0; 1652190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1662159SN/A 1672235SN/A#if FULL_SYSTEM 1682313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1692235SN/A 1702235SN/A // Not necessarily the best location for these... 1712235SN/A // Having an extra function just to read these is obnoxious 1722235SN/A virtual Tick readLastActivate() = 0; 1732235SN/A virtual Tick readLastSuspend() = 0; 1742254SN/A 1752254SN/A virtual void profileClear() = 0; 1762254SN/A virtual void profileSample() = 0; 1772235SN/A#endif 1782235SN/A 1792680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1802159SN/A 1812190SN/A virtual void clearArchRegs() = 0; 1822159SN/A 1832159SN/A // 1842159SN/A // New accessors for new decoder. 1852159SN/A // 1862190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1872159SN/A 1882455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1892159SN/A 1902455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1912159SN/A 1922190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 1932159SN/A 1942455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 1952159SN/A 1962455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 1972455SN/A 1987720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 1992159SN/A 2007720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2012159SN/A 2027720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2032159SN/A 2047720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2052159SN/A 2067720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2075260Sksewell@umich.edu 2084172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2094172Ssaidi@eecs.umich.edu 2102190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2112159SN/A 2124172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2132190SN/A 2143468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2152190SN/A 2166313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2176313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2186313Sgblack@eecs.umich.edu 2196221Snate@binkert.org virtual uint64_t 2206221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2216221Snate@binkert.org { 2226221Snate@binkert.org return 0; 2236221Snate@binkert.org } 2244661Sksewell@umich.edu 2256221Snate@binkert.org virtual void 2266221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2276221Snate@binkert.org { 2286221Snate@binkert.org } 2294661Sksewell@umich.edu 2302235SN/A // Also not necessarily the best location for these two. Hopefully will go 2312235SN/A // away once we decide upon where st cond failures goes. 2322190SN/A virtual unsigned readStCondFailures() = 0; 2332190SN/A 2342190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2352159SN/A 2362235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2372190SN/A virtual bool misspeculating() = 0; 2382190SN/A 2392159SN/A#if !FULL_SYSTEM 2402235SN/A // Same with st cond failures. 2412190SN/A virtual Counter readFuncExeInst() = 0; 2422834Sksewell@umich.edu 2434111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2444111Sgblack@eecs.umich.edu 2452834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2462834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2472834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2482834Sksewell@umich.edu virtual int exit() { return 1; }; 2492159SN/A#endif 2502525SN/A 2515217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2525217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2532159SN/A}; 2542159SN/A 2552682Sktlim@umich.edu/** 2562682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2572682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2582682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2592682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2602682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2612682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2622682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2632682Sktlim@umich.edu * simple_thread.hh for an example of this. 2642682Sktlim@umich.edu */ 2652680Sktlim@umich.edutemplate <class TC> 2662680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2672190SN/A{ 2682190SN/A public: 2692680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2702680Sktlim@umich.edu { actualTC = actual_tc; } 2712159SN/A 2722190SN/A private: 2732680Sktlim@umich.edu TC *actualTC; 2742SN/A 2752SN/A public: 2762SN/A 2772680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2782SN/A 2795712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2802SN/A 2815715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 2825715Shsul@eecs.umich.edu 2835715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 2845714Shsul@eecs.umich.edu 2855714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 2865714Shsul@eecs.umich.edu 2875714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 2885714Shsul@eecs.umich.edu 2896022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 2901917SN/A 2916022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 2922521SN/A 2938541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 2948541Sgblack@eecs.umich.edu 2954997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2964997Sgblack@eecs.umich.edu 2975803Snate@binkert.org#if FULL_SYSTEM 2983548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 2993548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3002654SN/A 3012680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3022521SN/A 3035499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 3043673Srdreslin@umich.edu 3055497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 3062SN/A#else 3072680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3082518SN/A 3092680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3102SN/A#endif 3112SN/A 3122680Sktlim@umich.edu Status status() const { return actualTC->status(); } 313595SN/A 3142680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3152SN/A 3162190SN/A /// Set the status to Active. Optional delay indicates number of 3172190SN/A /// cycles to wait before beginning execution. 3182680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3192SN/A 3202190SN/A /// Set the status to Suspended. 3215250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3222SN/A 3232190SN/A /// Set the status to Halted. 3245250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 325217SN/A 3261858SN/A#if FULL_SYSTEM 3272680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3282190SN/A#endif 3292190SN/A 3302680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3312680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3322190SN/A 3332680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3342190SN/A 3352680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3362190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3372680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3382190SN/A 3392235SN/A#if FULL_SYSTEM 3402680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3412235SN/A 3422680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3432680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3442254SN/A 3452680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3462680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3472235SN/A#endif 3482SN/A 3492190SN/A // @todo: Do I need this? 3502680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3512SN/A 3522680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 353716SN/A 3542SN/A // 3552SN/A // New accessors for new decoder. 3562SN/A // 3572SN/A uint64_t readIntReg(int reg_idx) 3582680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3592SN/A 3602455SN/A FloatReg readFloatReg(int reg_idx) 3612680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3622SN/A 3632455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3642680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3652SN/A 3662SN/A void setIntReg(int reg_idx, uint64_t val) 3672680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3682SN/A 3692455SN/A void setFloatReg(int reg_idx, FloatReg val) 3702680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3712SN/A 3722455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3732680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3742SN/A 3757720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 3762SN/A 3777720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 3782206SN/A 3797720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 3807720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 3817720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 3825260Sksewell@umich.edu 3837597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 3847597Sminkyu.jeong@arm.com 3857597Sminkyu.jeong@arm.com void setPredicate(bool val) 3867597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 3877597Sminkyu.jeong@arm.com 3884172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3894172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 3904172Ssaidi@eecs.umich.edu 3912159SN/A MiscReg readMiscReg(int misc_reg) 3922680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 3932SN/A 3944172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3954172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 3962SN/A 3973468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3982680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 3992SN/A 4006313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4016313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4026313Sgblack@eecs.umich.edu 4036313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4046313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4056313Sgblack@eecs.umich.edu 4062190SN/A unsigned readStCondFailures() 4072680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4082190SN/A 4092190SN/A void setStCondFailures(unsigned sc_failures) 4102680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4112SN/A 4122190SN/A // @todo: Fix this! 4132680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4142190SN/A 4151858SN/A#if !FULL_SYSTEM 4164111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4174111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4184111Sgblack@eecs.umich.edu 4192680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4202SN/A#endif 4212SN/A}; 4222SN/A 4232190SN/A#endif 424