thread_context.hh revision 6658
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 346329Sgblack@eecs.umich.edu#include "arch/registers.hh" 353453Sgblack@eecs.umich.edu#include "arch/types.hh" 366216Snate@binkert.org#include "base/types.hh" 371858SN/A#include "config/full_system.hh" 386658Snate@binkert.org#include "config/the_isa.hh" 392423SN/A#include "mem/request.hh" 406216Snate@binkert.org#include "sim/byteswap.hh" 412190SN/A#include "sim/faults.hh" 42217SN/A#include "sim/serialize.hh" 432SN/A 442190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 452190SN/A// DTB pointers. 463453Sgblack@eecs.umich.edunamespace TheISA 473453Sgblack@eecs.umich.edu{ 486022Sgblack@eecs.umich.edu class TLB; 493453Sgblack@eecs.umich.edu} 502190SN/Aclass BaseCPU; 512313SN/Aclass EndQuiesceEvent; 522235SN/Aclass Event; 532423SN/Aclass TranslatingPort; 542521SN/Aclass FunctionalPort; 552521SN/Aclass VirtualPort; 562190SN/Aclass Process; 572190SN/Aclass System; 583548Sgblack@eecs.umich.edunamespace TheISA { 593548Sgblack@eecs.umich.edu namespace Kernel { 603548Sgblack@eecs.umich.edu class Statistics; 613548Sgblack@eecs.umich.edu }; 622330SN/A}; 632SN/A 642680Sktlim@umich.edu/** 652680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 662680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 672680Sktlim@umich.edu * state that might be needed by external objects, ranging from 682680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 692680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 702680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 712680Sktlim@umich.edu * 722680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 732680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 742680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 752682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 762680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 772680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 782680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 792680Sktlim@umich.edu */ 802680Sktlim@umich.educlass ThreadContext 812SN/A{ 822107SN/A protected: 832107SN/A typedef TheISA::MachInst MachInst; 842190SN/A typedef TheISA::IntReg IntReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872159SN/A typedef TheISA::MiscReg MiscReg; 882SN/A public: 896029Ssteve.reinhardt@amd.com 90246SN/A enum Status 91246SN/A { 92246SN/A /// Running. Instructions should be executed only when 93246SN/A /// the context is in this state. 94246SN/A Active, 95246SN/A 96246SN/A /// Temporarily inactive. Entered while waiting for 972190SN/A /// synchronization, etc. 98246SN/A Suspended, 99246SN/A 100246SN/A /// Permanently shut down. Entered when target executes 101246SN/A /// m5exit pseudo-instruction. When all contexts enter 102246SN/A /// this state, the simulation will terminate. 103246SN/A Halted 104246SN/A }; 1052SN/A 1062680Sktlim@umich.edu virtual ~ThreadContext() { }; 1072423SN/A 1082190SN/A virtual BaseCPU *getCpuPtr() = 0; 109180SN/A 1105712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1112190SN/A 1125715Shsul@eecs.umich.edu virtual int threadId() = 0; 1135715Shsul@eecs.umich.edu 1145715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1155714Shsul@eecs.umich.edu 1165714Shsul@eecs.umich.edu virtual int contextId() = 0; 1175714Shsul@eecs.umich.edu 1185714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1195714Shsul@eecs.umich.edu 1206022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1212190SN/A 1226022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1232521SN/A 1244997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1254997Sgblack@eecs.umich.edu 1265803Snate@binkert.org#if FULL_SYSTEM 1273548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1282654SN/A 1292521SN/A virtual FunctionalPort *getPhysPort() = 0; 1302521SN/A 1315499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort() = 0; 1323673Srdreslin@umich.edu 1335497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) = 0; 1342190SN/A#else 1352518SN/A virtual TranslatingPort *getMemPort() = 0; 1362518SN/A 1372190SN/A virtual Process *getProcessPtr() = 0; 1382190SN/A#endif 1392190SN/A 1402190SN/A virtual Status status() const = 0; 1412159SN/A 1422235SN/A virtual void setStatus(Status new_status) = 0; 1432103SN/A 144393SN/A /// Set the status to Active. Optional delay indicates number of 145393SN/A /// cycles to wait before beginning execution. 1462190SN/A virtual void activate(int delay = 1) = 0; 147393SN/A 148393SN/A /// Set the status to Suspended. 1495250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 150393SN/A 151393SN/A /// Set the status to Halted. 1525250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1532159SN/A 1542159SN/A#if FULL_SYSTEM 1552190SN/A virtual void dumpFuncProfile() = 0; 1562159SN/A#endif 1572159SN/A 1582680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1592159SN/A 1602190SN/A virtual void regStats(const std::string &name) = 0; 1612159SN/A 1622190SN/A virtual void serialize(std::ostream &os) = 0; 1632190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1642159SN/A 1652235SN/A#if FULL_SYSTEM 1662313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1672235SN/A 1682235SN/A // Not necessarily the best location for these... 1692235SN/A // Having an extra function just to read these is obnoxious 1702235SN/A virtual Tick readLastActivate() = 0; 1712235SN/A virtual Tick readLastSuspend() = 0; 1722254SN/A 1732254SN/A virtual void profileClear() = 0; 1742254SN/A virtual void profileSample() = 0; 1752235SN/A#endif 1762235SN/A 1772235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1782254SN/A // However, may be quite useful in SPARC. 1792190SN/A virtual TheISA::MachInst getInst() = 0; 1802159SN/A 1812680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1822159SN/A 1832190SN/A virtual void clearArchRegs() = 0; 1842159SN/A 1852159SN/A // 1862159SN/A // New accessors for new decoder. 1872159SN/A // 1882190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1892159SN/A 1902455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1912159SN/A 1922455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1932159SN/A 1942190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 1952159SN/A 1962455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 1972159SN/A 1982455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 1992455SN/A 2002190SN/A virtual uint64_t readPC() = 0; 2012159SN/A 2022190SN/A virtual void setPC(uint64_t val) = 0; 2032159SN/A 2042190SN/A virtual uint64_t readNextPC() = 0; 2052159SN/A 2062190SN/A virtual void setNextPC(uint64_t val) = 0; 2072159SN/A 2082447SN/A virtual uint64_t readNextNPC() = 0; 2092447SN/A 2102447SN/A virtual void setNextNPC(uint64_t val) = 0; 2112447SN/A 2125260Sksewell@umich.edu virtual uint64_t readMicroPC() = 0; 2135260Sksewell@umich.edu 2145260Sksewell@umich.edu virtual void setMicroPC(uint64_t val) = 0; 2155260Sksewell@umich.edu 2165260Sksewell@umich.edu virtual uint64_t readNextMicroPC() = 0; 2175260Sksewell@umich.edu 2185260Sksewell@umich.edu virtual void setNextMicroPC(uint64_t val) = 0; 2195260Sksewell@umich.edu 2204172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2214172Ssaidi@eecs.umich.edu 2222190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2232159SN/A 2244172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2252190SN/A 2263468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2272190SN/A 2286313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2296313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2306313Sgblack@eecs.umich.edu 2316221Snate@binkert.org virtual uint64_t 2326221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2336221Snate@binkert.org { 2346221Snate@binkert.org return 0; 2356221Snate@binkert.org } 2364661Sksewell@umich.edu 2376221Snate@binkert.org virtual void 2386221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2396221Snate@binkert.org { 2406221Snate@binkert.org } 2414661Sksewell@umich.edu 2422235SN/A // Also not necessarily the best location for these two. Hopefully will go 2432235SN/A // away once we decide upon where st cond failures goes. 2442190SN/A virtual unsigned readStCondFailures() = 0; 2452190SN/A 2462190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2472159SN/A 2482235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2492190SN/A virtual bool misspeculating() = 0; 2502190SN/A 2512159SN/A#if !FULL_SYSTEM 2522235SN/A // Same with st cond failures. 2532190SN/A virtual Counter readFuncExeInst() = 0; 2542834Sksewell@umich.edu 2554111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2564111Sgblack@eecs.umich.edu 2572834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2582834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2592834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2602834Sksewell@umich.edu virtual int exit() { return 1; }; 2612159SN/A#endif 2622525SN/A 2635217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2645217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2652159SN/A}; 2662159SN/A 2672682Sktlim@umich.edu/** 2682682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2692682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2702682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2712682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2722682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2732682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2742682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2752682Sktlim@umich.edu * simple_thread.hh for an example of this. 2762682Sktlim@umich.edu */ 2772680Sktlim@umich.edutemplate <class TC> 2782680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2792190SN/A{ 2802190SN/A public: 2812680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2822680Sktlim@umich.edu { actualTC = actual_tc; } 2832159SN/A 2842190SN/A private: 2852680Sktlim@umich.edu TC *actualTC; 2862SN/A 2872SN/A public: 2882SN/A 2892680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2902SN/A 2915712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2922SN/A 2935715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 2945715Shsul@eecs.umich.edu 2955715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 2965714Shsul@eecs.umich.edu 2975714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 2985714Shsul@eecs.umich.edu 2995714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3005714Shsul@eecs.umich.edu 3016022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3021917SN/A 3036022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3042521SN/A 3054997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3064997Sgblack@eecs.umich.edu 3075803Snate@binkert.org#if FULL_SYSTEM 3083548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3093548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3102654SN/A 3112680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3122521SN/A 3135499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 3143673Srdreslin@umich.edu 3155497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 3162SN/A#else 3172680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3182518SN/A 3192680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3202SN/A#endif 3212SN/A 3222680Sktlim@umich.edu Status status() const { return actualTC->status(); } 323595SN/A 3242680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3252SN/A 3262190SN/A /// Set the status to Active. Optional delay indicates number of 3272190SN/A /// cycles to wait before beginning execution. 3282680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3292SN/A 3302190SN/A /// Set the status to Suspended. 3315250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3322SN/A 3332190SN/A /// Set the status to Halted. 3345250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 335217SN/A 3361858SN/A#if FULL_SYSTEM 3372680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3382190SN/A#endif 3392190SN/A 3402680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3412680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3422190SN/A 3432680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3442190SN/A 3452680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3462190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3472680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3482190SN/A 3492235SN/A#if FULL_SYSTEM 3502680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3512235SN/A 3522680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3532680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3542254SN/A 3552680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3562680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3572235SN/A#endif 3582190SN/A // @todo: Do I need this? 3592680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3602SN/A 3612190SN/A // @todo: Do I need this? 3622680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3632SN/A 3642680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 365716SN/A 3662SN/A // 3672SN/A // New accessors for new decoder. 3682SN/A // 3692SN/A uint64_t readIntReg(int reg_idx) 3702680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3712SN/A 3722455SN/A FloatReg readFloatReg(int reg_idx) 3732680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3742SN/A 3752455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3762680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3772SN/A 3782SN/A void setIntReg(int reg_idx, uint64_t val) 3792680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3802SN/A 3812455SN/A void setFloatReg(int reg_idx, FloatReg val) 3822680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3832SN/A 3842455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3852680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3862SN/A 3872680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 3882SN/A 3892680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 3902206SN/A 3912680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 3922252SN/A 3932680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 3942SN/A 3952680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 3962447SN/A 3972680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 3982447SN/A 3995260Sksewell@umich.edu uint64_t readMicroPC() { return actualTC->readMicroPC(); } 4005260Sksewell@umich.edu 4015260Sksewell@umich.edu void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 4025260Sksewell@umich.edu 4035260Sksewell@umich.edu uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 4045260Sksewell@umich.edu 4055592Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 4065260Sksewell@umich.edu 4074172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4084172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4094172Ssaidi@eecs.umich.edu 4102159SN/A MiscReg readMiscReg(int misc_reg) 4112680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4122SN/A 4134172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4144172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4152SN/A 4163468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4172680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4182SN/A 4196313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4206313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4216313Sgblack@eecs.umich.edu 4226313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4236313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4246313Sgblack@eecs.umich.edu 4252190SN/A unsigned readStCondFailures() 4262680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4272190SN/A 4282190SN/A void setStCondFailures(unsigned sc_failures) 4292680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4302SN/A 4312190SN/A // @todo: Fix this! 4322680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4332190SN/A 4341858SN/A#if !FULL_SYSTEM 4354111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4364111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4374111Sgblack@eecs.umich.edu 4382680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4392SN/A#endif 4402SN/A}; 4412SN/A 4422190SN/A#endif 443