thread_context.hh revision 5499
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 353453Sgblack@eecs.umich.edu#include "arch/types.hh" 361858SN/A#include "config/full_system.hh" 372423SN/A#include "mem/request.hh" 382190SN/A#include "sim/faults.hh" 3956SN/A#include "sim/host.hh" 40217SN/A#include "sim/serialize.hh" 413776Sgblack@eecs.umich.edu#include "sim/syscallreturn.hh" 422036SN/A#include "sim/byteswap.hh" 432SN/A 442190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 452190SN/A// DTB pointers. 463453Sgblack@eecs.umich.edunamespace TheISA 473453Sgblack@eecs.umich.edu{ 483453Sgblack@eecs.umich.edu class DTB; 493453Sgblack@eecs.umich.edu class ITB; 503453Sgblack@eecs.umich.edu} 512190SN/Aclass BaseCPU; 522313SN/Aclass EndQuiesceEvent; 532235SN/Aclass Event; 542423SN/Aclass TranslatingPort; 552521SN/Aclass FunctionalPort; 562521SN/Aclass VirtualPort; 572190SN/Aclass Process; 582190SN/Aclass System; 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642SN/A 652680Sktlim@umich.edu/** 662680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 672680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 682680Sktlim@umich.edu * state that might be needed by external objects, ranging from 692680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 702680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 712680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 722680Sktlim@umich.edu * 732680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 742680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 752680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 762682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 772680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 782680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 792680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 802680Sktlim@umich.edu */ 812680Sktlim@umich.educlass ThreadContext 822SN/A{ 832107SN/A protected: 842107SN/A typedef TheISA::RegFile RegFile; 852107SN/A typedef TheISA::MachInst MachInst; 862190SN/A typedef TheISA::IntReg IntReg; 872455SN/A typedef TheISA::FloatReg FloatReg; 882455SN/A typedef TheISA::FloatRegBits FloatRegBits; 892107SN/A typedef TheISA::MiscRegFile MiscRegFile; 902159SN/A typedef TheISA::MiscReg MiscReg; 912SN/A public: 92246SN/A enum Status 93246SN/A { 94246SN/A /// Initialized but not running yet. All CPUs start in 95246SN/A /// this state, but most transition to Active on cycle 1. 96246SN/A /// In MP or SMT systems, non-primary contexts will stay 97246SN/A /// in this state until a thread is assigned to them. 98246SN/A Unallocated, 99246SN/A 100246SN/A /// Running. Instructions should be executed only when 101246SN/A /// the context is in this state. 102246SN/A Active, 103246SN/A 104246SN/A /// Temporarily inactive. Entered while waiting for 1052190SN/A /// synchronization, etc. 106246SN/A Suspended, 107246SN/A 108246SN/A /// Permanently shut down. Entered when target executes 109246SN/A /// m5exit pseudo-instruction. When all contexts enter 110246SN/A /// this state, the simulation will terminate. 111246SN/A Halted 112246SN/A }; 1132SN/A 1142680Sktlim@umich.edu virtual ~ThreadContext() { }; 1152423SN/A 1162190SN/A virtual BaseCPU *getCpuPtr() = 0; 117180SN/A 1182190SN/A virtual void setCpuId(int id) = 0; 1192190SN/A 1202190SN/A virtual int readCpuId() = 0; 1212190SN/A 1223453Sgblack@eecs.umich.edu virtual TheISA::ITB *getITBPtr() = 0; 1232190SN/A 1243453Sgblack@eecs.umich.edu virtual TheISA::DTB *getDTBPtr() = 0; 1252521SN/A 1264997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1274997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1284997Sgblack@eecs.umich.edu 1293548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1302654SN/A 1312521SN/A virtual FunctionalPort *getPhysPort() = 0; 1322521SN/A 1335499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort() = 0; 1343673Srdreslin@umich.edu 1355497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) = 0; 1362190SN/A#else 1372518SN/A virtual TranslatingPort *getMemPort() = 0; 1382518SN/A 1392190SN/A virtual Process *getProcessPtr() = 0; 1402190SN/A#endif 1412190SN/A 1422190SN/A virtual Status status() const = 0; 1432159SN/A 1442235SN/A virtual void setStatus(Status new_status) = 0; 1452103SN/A 146393SN/A /// Set the status to Active. Optional delay indicates number of 147393SN/A /// cycles to wait before beginning execution. 1482190SN/A virtual void activate(int delay = 1) = 0; 149393SN/A 150393SN/A /// Set the status to Suspended. 1515250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 152393SN/A 153393SN/A /// Set the status to Unallocated. 1542875Sksewell@umich.edu virtual void deallocate(int delay = 0) = 0; 155393SN/A 156393SN/A /// Set the status to Halted. 1575250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1582159SN/A 1592159SN/A#if FULL_SYSTEM 1602190SN/A virtual void dumpFuncProfile() = 0; 1612159SN/A#endif 1622159SN/A 1632680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1642159SN/A 1652190SN/A virtual void regStats(const std::string &name) = 0; 1662159SN/A 1672190SN/A virtual void serialize(std::ostream &os) = 0; 1682190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1692159SN/A 1702235SN/A#if FULL_SYSTEM 1712313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1722235SN/A 1732235SN/A // Not necessarily the best location for these... 1742235SN/A // Having an extra function just to read these is obnoxious 1752235SN/A virtual Tick readLastActivate() = 0; 1762235SN/A virtual Tick readLastSuspend() = 0; 1772254SN/A 1782254SN/A virtual void profileClear() = 0; 1792254SN/A virtual void profileSample() = 0; 1802235SN/A#endif 1812235SN/A 1822190SN/A virtual int getThreadNum() = 0; 1832159SN/A 1842235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1852254SN/A // However, may be quite useful in SPARC. 1862190SN/A virtual TheISA::MachInst getInst() = 0; 1872159SN/A 1882680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1892159SN/A 1902190SN/A virtual void clearArchRegs() = 0; 1912159SN/A 1922159SN/A // 1932159SN/A // New accessors for new decoder. 1942159SN/A // 1952190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1962159SN/A 1972455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1982159SN/A 1992455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2002159SN/A 2012455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 2022455SN/A 2032455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2042159SN/A 2052190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2062159SN/A 2072455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2082159SN/A 2092455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2102159SN/A 2112455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2122455SN/A 2132455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2142159SN/A 2152190SN/A virtual uint64_t readPC() = 0; 2162159SN/A 2172190SN/A virtual void setPC(uint64_t val) = 0; 2182159SN/A 2192190SN/A virtual uint64_t readNextPC() = 0; 2202159SN/A 2212190SN/A virtual void setNextPC(uint64_t val) = 0; 2222159SN/A 2232447SN/A virtual uint64_t readNextNPC() = 0; 2242447SN/A 2252447SN/A virtual void setNextNPC(uint64_t val) = 0; 2262447SN/A 2275260Sksewell@umich.edu virtual uint64_t readMicroPC() = 0; 2285260Sksewell@umich.edu 2295260Sksewell@umich.edu virtual void setMicroPC(uint64_t val) = 0; 2305260Sksewell@umich.edu 2315260Sksewell@umich.edu virtual uint64_t readNextMicroPC() = 0; 2325260Sksewell@umich.edu 2335260Sksewell@umich.edu virtual void setNextMicroPC(uint64_t val) = 0; 2345260Sksewell@umich.edu 2354172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2364172Ssaidi@eecs.umich.edu 2372190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2382159SN/A 2394172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2402190SN/A 2413468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2422190SN/A 2434661Sksewell@umich.edu virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } 2444661Sksewell@umich.edu 2454661Sksewell@umich.edu virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; 2464661Sksewell@umich.edu 2472235SN/A // Also not necessarily the best location for these two. Hopefully will go 2482235SN/A // away once we decide upon where st cond failures goes. 2492190SN/A virtual unsigned readStCondFailures() = 0; 2502190SN/A 2512190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2522159SN/A 2532235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2542190SN/A virtual bool misspeculating() = 0; 2552190SN/A 2562159SN/A#if !FULL_SYSTEM 2572190SN/A virtual IntReg getSyscallArg(int i) = 0; 2582159SN/A 2592159SN/A // used to shift args for indirect syscall 2602190SN/A virtual void setSyscallArg(int i, IntReg val) = 0; 2612159SN/A 2622190SN/A virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2632159SN/A 2642235SN/A // Same with st cond failures. 2652190SN/A virtual Counter readFuncExeInst() = 0; 2662834Sksewell@umich.edu 2674111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2684111Sgblack@eecs.umich.edu 2692834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2702834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2712834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2722834Sksewell@umich.edu virtual int exit() { return 1; }; 2732159SN/A#endif 2742525SN/A 2752972Sgblack@eecs.umich.edu virtual void changeRegFileContext(TheISA::RegContextParam param, 2762972Sgblack@eecs.umich.edu TheISA::RegContextVal val) = 0; 2775217Ssaidi@eecs.umich.edu 2785217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2795217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2802159SN/A}; 2812159SN/A 2822682Sktlim@umich.edu/** 2832682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2842682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2852682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2862682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2872682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2882682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2892682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2902682Sktlim@umich.edu * simple_thread.hh for an example of this. 2912682Sktlim@umich.edu */ 2922680Sktlim@umich.edutemplate <class TC> 2932680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2942190SN/A{ 2952190SN/A public: 2962680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2972680Sktlim@umich.edu { actualTC = actual_tc; } 2982159SN/A 2992190SN/A private: 3002680Sktlim@umich.edu TC *actualTC; 3012SN/A 3022SN/A public: 3032SN/A 3042680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3052SN/A 3062680Sktlim@umich.edu void setCpuId(int id) { actualTC->setCpuId(id); } 307716SN/A 3082680Sktlim@umich.edu int readCpuId() { return actualTC->readCpuId(); } 3092SN/A 3103453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 3111917SN/A 3123453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 3132521SN/A 3144997Sgblack@eecs.umich.edu#if FULL_SYSTEM 3154997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3164997Sgblack@eecs.umich.edu 3173548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3183548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3192654SN/A 3202680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3212521SN/A 3225499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 3233673Srdreslin@umich.edu 3245497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 3252SN/A#else 3262680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3272518SN/A 3282680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3292SN/A#endif 3302SN/A 3312680Sktlim@umich.edu Status status() const { return actualTC->status(); } 332595SN/A 3332680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3342SN/A 3352190SN/A /// Set the status to Active. Optional delay indicates number of 3362190SN/A /// cycles to wait before beginning execution. 3372680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3382SN/A 3392190SN/A /// Set the status to Suspended. 3405250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3412SN/A 3422190SN/A /// Set the status to Unallocated. 3432875Sksewell@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(); } 3442SN/A 3452190SN/A /// Set the status to Halted. 3465250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 347217SN/A 3481858SN/A#if FULL_SYSTEM 3492680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3502190SN/A#endif 3512190SN/A 3522680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3532680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3542190SN/A 3552680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3562190SN/A 3572680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3582190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3592680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3602190SN/A 3612235SN/A#if FULL_SYSTEM 3622680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3632235SN/A 3642680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3652680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3662254SN/A 3672680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3682680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3692235SN/A#endif 3702235SN/A 3712680Sktlim@umich.edu int getThreadNum() { return actualTC->getThreadNum(); } 3722190SN/A 3732190SN/A // @todo: Do I need this? 3742680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3752SN/A 3762190SN/A // @todo: Do I need this? 3772680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3782SN/A 3792680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 380716SN/A 3812SN/A // 3822SN/A // New accessors for new decoder. 3832SN/A // 3842SN/A uint64_t readIntReg(int reg_idx) 3852680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3862SN/A 3872455SN/A FloatReg readFloatReg(int reg_idx, int width) 3882680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3892SN/A 3902455SN/A FloatReg readFloatReg(int reg_idx) 3912680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3922SN/A 3932455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3942680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3952455SN/A 3962455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3972680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3982SN/A 3992SN/A void setIntReg(int reg_idx, uint64_t val) 4002680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 4012SN/A 4022455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 4032680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 4042SN/A 4052455SN/A void setFloatReg(int reg_idx, FloatReg val) 4062680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4072SN/A 4082455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 4092680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 4102455SN/A 4112455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4122680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4132SN/A 4142680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 4152SN/A 4162680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 4172206SN/A 4182680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4192252SN/A 4202680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4212SN/A 4222680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4232447SN/A 4242680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4252447SN/A 4265260Sksewell@umich.edu uint64_t readMicroPC() { return actualTC->readMicroPC(); } 4275260Sksewell@umich.edu 4285260Sksewell@umich.edu void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 4295260Sksewell@umich.edu 4305260Sksewell@umich.edu uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 4315260Sksewell@umich.edu 4325260Sksewell@umich.edu void setNextMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 4335260Sksewell@umich.edu 4344172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4354172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4364172Ssaidi@eecs.umich.edu 4372159SN/A MiscReg readMiscReg(int misc_reg) 4382680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4392SN/A 4404172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4414172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4422SN/A 4433468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4442680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4452SN/A 4462190SN/A unsigned readStCondFailures() 4472680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4482190SN/A 4492190SN/A void setStCondFailures(unsigned sc_failures) 4502680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4512SN/A 4522190SN/A // @todo: Fix this! 4532680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4542190SN/A 4551858SN/A#if !FULL_SYSTEM 4562680Sktlim@umich.edu IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 457360SN/A 458360SN/A // used to shift args for indirect syscall 4592190SN/A void setSyscallArg(int i, IntReg val) 4602680Sktlim@umich.edu { actualTC->setSyscallArg(i, val); } 461360SN/A 4621450SN/A void setSyscallReturn(SyscallReturn return_value) 4632680Sktlim@umich.edu { actualTC->setSyscallReturn(return_value); } 464360SN/A 4654111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4664111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4674111Sgblack@eecs.umich.edu 4682680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4692SN/A#endif 4702525SN/A 4712972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4722972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4732525SN/A { 4742680Sktlim@umich.edu actualTC->changeRegFileContext(param, val); 4752525SN/A } 4762SN/A}; 4772SN/A 4782190SN/A#endif 479