thread_context.hh revision 3548
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 352972Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 363453Sgblack@eecs.umich.edu#include "arch/types.hh" 371858SN/A#include "config/full_system.hh" 382423SN/A#include "mem/request.hh" 392190SN/A#include "sim/faults.hh" 4056SN/A#include "sim/host.hh" 41217SN/A#include "sim/serialize.hh" 422036SN/A#include "sim/byteswap.hh" 432SN/A 442190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 452190SN/A// DTB pointers. 463453Sgblack@eecs.umich.edunamespace TheISA 473453Sgblack@eecs.umich.edu{ 483453Sgblack@eecs.umich.edu class DTB; 493453Sgblack@eecs.umich.edu class ITB; 503453Sgblack@eecs.umich.edu} 512190SN/Aclass BaseCPU; 522313SN/Aclass EndQuiesceEvent; 532235SN/Aclass Event; 542423SN/Aclass TranslatingPort; 552521SN/Aclass FunctionalPort; 562521SN/Aclass VirtualPort; 572190SN/Aclass Process; 582190SN/Aclass System; 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642SN/A 652680Sktlim@umich.edu/** 662680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 672680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 682680Sktlim@umich.edu * state that might be needed by external objects, ranging from 692680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 702680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 712680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 722680Sktlim@umich.edu * 732680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 742680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 752680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 762682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 772680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 782680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 792680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 802680Sktlim@umich.edu */ 812680Sktlim@umich.educlass ThreadContext 822SN/A{ 832107SN/A protected: 842107SN/A typedef TheISA::RegFile RegFile; 852107SN/A typedef TheISA::MachInst MachInst; 862190SN/A typedef TheISA::IntReg IntReg; 872455SN/A typedef TheISA::FloatReg FloatReg; 882455SN/A typedef TheISA::FloatRegBits FloatRegBits; 892107SN/A typedef TheISA::MiscRegFile MiscRegFile; 902159SN/A typedef TheISA::MiscReg MiscReg; 912SN/A public: 92246SN/A enum Status 93246SN/A { 94246SN/A /// Initialized but not running yet. All CPUs start in 95246SN/A /// this state, but most transition to Active on cycle 1. 96246SN/A /// In MP or SMT systems, non-primary contexts will stay 97246SN/A /// in this state until a thread is assigned to them. 98246SN/A Unallocated, 99246SN/A 100246SN/A /// Running. Instructions should be executed only when 101246SN/A /// the context is in this state. 102246SN/A Active, 103246SN/A 104246SN/A /// Temporarily inactive. Entered while waiting for 1052190SN/A /// synchronization, etc. 106246SN/A Suspended, 107246SN/A 108246SN/A /// Permanently shut down. Entered when target executes 109246SN/A /// m5exit pseudo-instruction. When all contexts enter 110246SN/A /// this state, the simulation will terminate. 111246SN/A Halted 112246SN/A }; 1132SN/A 1142680Sktlim@umich.edu virtual ~ThreadContext() { }; 1152423SN/A 1162190SN/A virtual BaseCPU *getCpuPtr() = 0; 117180SN/A 1182190SN/A virtual void setCpuId(int id) = 0; 1192190SN/A 1202190SN/A virtual int readCpuId() = 0; 1212190SN/A 1222190SN/A#if FULL_SYSTEM 1232190SN/A virtual System *getSystemPtr() = 0; 1242190SN/A 1253453Sgblack@eecs.umich.edu virtual TheISA::ITB *getITBPtr() = 0; 1262190SN/A 1273453Sgblack@eecs.umich.edu virtual TheISA::DTB *getDTBPtr() = 0; 1282521SN/A 1293548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1302654SN/A 1312521SN/A virtual FunctionalPort *getPhysPort() = 0; 1322521SN/A 1332680Sktlim@umich.edu virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 1342521SN/A 1352521SN/A virtual void delVirtPort(VirtualPort *vp) = 0; 1362190SN/A#else 1372518SN/A virtual TranslatingPort *getMemPort() = 0; 1382518SN/A 1392190SN/A virtual Process *getProcessPtr() = 0; 1402190SN/A#endif 1412190SN/A 1422190SN/A virtual Status status() const = 0; 1432159SN/A 1442235SN/A virtual void setStatus(Status new_status) = 0; 1452103SN/A 146393SN/A /// Set the status to Active. Optional delay indicates number of 147393SN/A /// cycles to wait before beginning execution. 1482190SN/A virtual void activate(int delay = 1) = 0; 149393SN/A 150393SN/A /// Set the status to Suspended. 1512190SN/A virtual void suspend() = 0; 152393SN/A 153393SN/A /// Set the status to Unallocated. 1542875Sksewell@umich.edu virtual void deallocate(int delay = 0) = 0; 155393SN/A 156393SN/A /// Set the status to Halted. 1572190SN/A virtual void halt() = 0; 1582159SN/A 1592159SN/A#if FULL_SYSTEM 1602190SN/A virtual void dumpFuncProfile() = 0; 1612159SN/A#endif 1622159SN/A 1632680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1642159SN/A 1652190SN/A virtual void regStats(const std::string &name) = 0; 1662159SN/A 1672190SN/A virtual void serialize(std::ostream &os) = 0; 1682190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1692159SN/A 1702235SN/A#if FULL_SYSTEM 1712313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1722235SN/A 1732235SN/A // Not necessarily the best location for these... 1742235SN/A // Having an extra function just to read these is obnoxious 1752235SN/A virtual Tick readLastActivate() = 0; 1762235SN/A virtual Tick readLastSuspend() = 0; 1772254SN/A 1782254SN/A virtual void profileClear() = 0; 1792254SN/A virtual void profileSample() = 0; 1802235SN/A#endif 1812235SN/A 1822190SN/A virtual int getThreadNum() = 0; 1832159SN/A 1842235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1852254SN/A // However, may be quite useful in SPARC. 1862190SN/A virtual TheISA::MachInst getInst() = 0; 1872159SN/A 1882680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1892159SN/A 1902190SN/A virtual void clearArchRegs() = 0; 1912159SN/A 1922159SN/A // 1932159SN/A // New accessors for new decoder. 1942159SN/A // 1952190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1962159SN/A 1972455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1982159SN/A 1992455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2002159SN/A 2012455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 2022455SN/A 2032455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2042159SN/A 2052190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2062159SN/A 2072455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2082159SN/A 2092455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2102159SN/A 2112455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2122455SN/A 2132455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2142159SN/A 2152190SN/A virtual uint64_t readPC() = 0; 2162159SN/A 2172190SN/A virtual void setPC(uint64_t val) = 0; 2182159SN/A 2192190SN/A virtual uint64_t readNextPC() = 0; 2202159SN/A 2212190SN/A virtual void setNextPC(uint64_t val) = 0; 2222159SN/A 2232447SN/A virtual uint64_t readNextNPC() = 0; 2242447SN/A 2252447SN/A virtual void setNextNPC(uint64_t val) = 0; 2262447SN/A 2272190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2282159SN/A 2293468Sgblack@eecs.umich.edu virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0; 2302190SN/A 2313468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2322190SN/A 2333468Sgblack@eecs.umich.edu virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 2342190SN/A 2352235SN/A // Also not necessarily the best location for these two. Hopefully will go 2362235SN/A // away once we decide upon where st cond failures goes. 2372190SN/A virtual unsigned readStCondFailures() = 0; 2382190SN/A 2392190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2402159SN/A 2412235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2422190SN/A virtual bool misspeculating() = 0; 2432190SN/A 2442159SN/A#if !FULL_SYSTEM 2452190SN/A virtual IntReg getSyscallArg(int i) = 0; 2462159SN/A 2472159SN/A // used to shift args for indirect syscall 2482190SN/A virtual void setSyscallArg(int i, IntReg val) = 0; 2492159SN/A 2502190SN/A virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2512159SN/A 2522235SN/A // Same with st cond failures. 2532190SN/A virtual Counter readFuncExeInst() = 0; 2542834Sksewell@umich.edu 2552834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2562834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2572834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2582834Sksewell@umich.edu virtual int exit() { return 1; }; 2592159SN/A#endif 2602525SN/A 2612972Sgblack@eecs.umich.edu virtual void changeRegFileContext(TheISA::RegContextParam param, 2622972Sgblack@eecs.umich.edu TheISA::RegContextVal val) = 0; 2632159SN/A}; 2642159SN/A 2652682Sktlim@umich.edu/** 2662682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2672682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2682682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2692682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2702682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2712682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2722682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2732682Sktlim@umich.edu * simple_thread.hh for an example of this. 2742682Sktlim@umich.edu */ 2752680Sktlim@umich.edutemplate <class TC> 2762680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2772190SN/A{ 2782190SN/A public: 2792680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2802680Sktlim@umich.edu { actualTC = actual_tc; } 2812159SN/A 2822190SN/A private: 2832680Sktlim@umich.edu TC *actualTC; 2842SN/A 2852SN/A public: 2862SN/A 2872680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2882SN/A 2892680Sktlim@umich.edu void setCpuId(int id) { actualTC->setCpuId(id); } 290716SN/A 2912680Sktlim@umich.edu int readCpuId() { return actualTC->readCpuId(); } 2922SN/A 2931858SN/A#if FULL_SYSTEM 2942680Sktlim@umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2952SN/A 2963453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 2971917SN/A 2983453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 2992521SN/A 3003548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3013548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3022654SN/A 3032680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3042521SN/A 3052680Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 3062521SN/A 3072680Sktlim@umich.edu void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 3082SN/A#else 3092680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3102518SN/A 3112680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3122SN/A#endif 3132SN/A 3142680Sktlim@umich.edu Status status() const { return actualTC->status(); } 315595SN/A 3162680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3172SN/A 3182190SN/A /// Set the status to Active. Optional delay indicates number of 3192190SN/A /// cycles to wait before beginning execution. 3202680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3212SN/A 3222190SN/A /// Set the status to Suspended. 3232680Sktlim@umich.edu void suspend() { actualTC->suspend(); } 3242SN/A 3252190SN/A /// Set the status to Unallocated. 3262875Sksewell@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(); } 3272SN/A 3282190SN/A /// Set the status to Halted. 3292680Sktlim@umich.edu void halt() { actualTC->halt(); } 330217SN/A 3311858SN/A#if FULL_SYSTEM 3322680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3332190SN/A#endif 3342190SN/A 3352680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3362680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3372190SN/A 3382680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3392190SN/A 3402680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3412190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3422680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3432190SN/A 3442235SN/A#if FULL_SYSTEM 3452680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3462235SN/A 3472680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3482680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3492254SN/A 3502680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3512680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3522235SN/A#endif 3532235SN/A 3542680Sktlim@umich.edu int getThreadNum() { return actualTC->getThreadNum(); } 3552190SN/A 3562190SN/A // @todo: Do I need this? 3572680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3582SN/A 3592190SN/A // @todo: Do I need this? 3602680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3612SN/A 3622680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 363716SN/A 3642SN/A // 3652SN/A // New accessors for new decoder. 3662SN/A // 3672SN/A uint64_t readIntReg(int reg_idx) 3682680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3692SN/A 3702455SN/A FloatReg readFloatReg(int reg_idx, int width) 3712680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3722SN/A 3732455SN/A FloatReg readFloatReg(int reg_idx) 3742680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3752SN/A 3762455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3772680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3782455SN/A 3792455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3802680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3812SN/A 3822SN/A void setIntReg(int reg_idx, uint64_t val) 3832680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3842SN/A 3852455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3862680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3872SN/A 3882455SN/A void setFloatReg(int reg_idx, FloatReg val) 3892680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3902SN/A 3912455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 3922680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 3932455SN/A 3942455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3952680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3962SN/A 3972680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 3982SN/A 3992680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 4002206SN/A 4012680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4022252SN/A 4032680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4042SN/A 4052680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4062447SN/A 4072680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4082447SN/A 4092159SN/A MiscReg readMiscReg(int misc_reg) 4102680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4112SN/A 4123468Sgblack@eecs.umich.edu MiscReg readMiscRegWithEffect(int misc_reg) 4133468Sgblack@eecs.umich.edu { return actualTC->readMiscRegWithEffect(misc_reg); } 4142SN/A 4153468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4162680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4172SN/A 4183468Sgblack@eecs.umich.edu void setMiscRegWithEffect(int misc_reg, const MiscReg &val) 4192680Sktlim@umich.edu { return actualTC->setMiscRegWithEffect(misc_reg, val); } 4202190SN/A 4212190SN/A unsigned readStCondFailures() 4222680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4232190SN/A 4242190SN/A void setStCondFailures(unsigned sc_failures) 4252680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4262SN/A 4272190SN/A // @todo: Fix this! 4282680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4292190SN/A 4301858SN/A#if !FULL_SYSTEM 4312680Sktlim@umich.edu IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 432360SN/A 433360SN/A // used to shift args for indirect syscall 4342190SN/A void setSyscallArg(int i, IntReg val) 4352680Sktlim@umich.edu { actualTC->setSyscallArg(i, val); } 436360SN/A 4371450SN/A void setSyscallReturn(SyscallReturn return_value) 4382680Sktlim@umich.edu { actualTC->setSyscallReturn(return_value); } 439360SN/A 4402680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4412SN/A#endif 4422525SN/A 4432972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4442972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4452525SN/A { 4462680Sktlim@umich.edu actualTC->changeRegFileContext(param, val); 4472525SN/A } 4482SN/A}; 4492SN/A 4502190SN/A#endif 451