thread_context.hh revision 3453
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 352972Sgblack@eecs.umich.edu#include "arch/syscallreturn.hh" 363453Sgblack@eecs.umich.edu#include "arch/types.hh" 371858SN/A#include "config/full_system.hh" 382423SN/A#include "mem/request.hh" 392190SN/A#include "sim/faults.hh" 4056SN/A#include "sim/host.hh" 41217SN/A#include "sim/serialize.hh" 422036SN/A#include "sim/byteswap.hh" 432SN/A 442190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 452190SN/A// DTB pointers. 463453Sgblack@eecs.umich.edunamespace TheISA 473453Sgblack@eecs.umich.edu{ 483453Sgblack@eecs.umich.edu class DTB; 493453Sgblack@eecs.umich.edu class ITB; 503453Sgblack@eecs.umich.edu} 512190SN/Aclass BaseCPU; 522313SN/Aclass EndQuiesceEvent; 532235SN/Aclass Event; 542423SN/Aclass TranslatingPort; 552521SN/Aclass FunctionalPort; 562521SN/Aclass VirtualPort; 572190SN/Aclass Process; 582190SN/Aclass System; 592330SN/Anamespace Kernel { 602330SN/A class Statistics; 612330SN/A}; 622SN/A 632680Sktlim@umich.edu/** 642680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 652680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 662680Sktlim@umich.edu * state that might be needed by external objects, ranging from 672680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 682680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 692680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 702680Sktlim@umich.edu * 712680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 722680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 732680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 742682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 752680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 762680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 772680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 782680Sktlim@umich.edu */ 792680Sktlim@umich.educlass ThreadContext 802SN/A{ 812107SN/A protected: 822107SN/A typedef TheISA::RegFile RegFile; 832107SN/A typedef TheISA::MachInst MachInst; 842190SN/A typedef TheISA::IntReg IntReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872107SN/A typedef TheISA::MiscRegFile MiscRegFile; 882159SN/A typedef TheISA::MiscReg MiscReg; 892SN/A public: 90246SN/A enum Status 91246SN/A { 92246SN/A /// Initialized but not running yet. All CPUs start in 93246SN/A /// this state, but most transition to Active on cycle 1. 94246SN/A /// In MP or SMT systems, non-primary contexts will stay 95246SN/A /// in this state until a thread is assigned to them. 96246SN/A Unallocated, 97246SN/A 98246SN/A /// Running. Instructions should be executed only when 99246SN/A /// the context is in this state. 100246SN/A Active, 101246SN/A 102246SN/A /// Temporarily inactive. Entered while waiting for 1032190SN/A /// synchronization, etc. 104246SN/A Suspended, 105246SN/A 106246SN/A /// Permanently shut down. Entered when target executes 107246SN/A /// m5exit pseudo-instruction. When all contexts enter 108246SN/A /// this state, the simulation will terminate. 109246SN/A Halted 110246SN/A }; 1112SN/A 1122680Sktlim@umich.edu virtual ~ThreadContext() { }; 1132423SN/A 1142190SN/A virtual BaseCPU *getCpuPtr() = 0; 115180SN/A 1162190SN/A virtual void setCpuId(int id) = 0; 1172190SN/A 1182190SN/A virtual int readCpuId() = 0; 1192190SN/A 1202190SN/A#if FULL_SYSTEM 1212190SN/A virtual System *getSystemPtr() = 0; 1222190SN/A 1233453Sgblack@eecs.umich.edu virtual TheISA::ITB *getITBPtr() = 0; 1242190SN/A 1253453Sgblack@eecs.umich.edu virtual TheISA::DTB *getDTBPtr() = 0; 1262521SN/A 1272330SN/A virtual Kernel::Statistics *getKernelStats() = 0; 1282654SN/A 1292521SN/A virtual FunctionalPort *getPhysPort() = 0; 1302521SN/A 1312680Sktlim@umich.edu virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 1322521SN/A 1332521SN/A virtual void delVirtPort(VirtualPort *vp) = 0; 1342190SN/A#else 1352518SN/A virtual TranslatingPort *getMemPort() = 0; 1362518SN/A 1372190SN/A virtual Process *getProcessPtr() = 0; 1382190SN/A#endif 1392190SN/A 1402190SN/A virtual Status status() const = 0; 1412159SN/A 1422235SN/A virtual void setStatus(Status new_status) = 0; 1432103SN/A 144393SN/A /// Set the status to Active. Optional delay indicates number of 145393SN/A /// cycles to wait before beginning execution. 1462190SN/A virtual void activate(int delay = 1) = 0; 147393SN/A 148393SN/A /// Set the status to Suspended. 1492190SN/A virtual void suspend() = 0; 150393SN/A 151393SN/A /// Set the status to Unallocated. 1522875Sksewell@umich.edu virtual void deallocate(int delay = 0) = 0; 153393SN/A 154393SN/A /// Set the status to Halted. 1552190SN/A virtual void halt() = 0; 1562159SN/A 1572159SN/A#if FULL_SYSTEM 1582190SN/A virtual void dumpFuncProfile() = 0; 1592159SN/A#endif 1602159SN/A 1612680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1622159SN/A 1632190SN/A virtual void regStats(const std::string &name) = 0; 1642159SN/A 1652190SN/A virtual void serialize(std::ostream &os) = 0; 1662190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1672159SN/A 1682235SN/A#if FULL_SYSTEM 1692313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1702235SN/A 1712235SN/A // Not necessarily the best location for these... 1722235SN/A // Having an extra function just to read these is obnoxious 1732235SN/A virtual Tick readLastActivate() = 0; 1742235SN/A virtual Tick readLastSuspend() = 0; 1752254SN/A 1762254SN/A virtual void profileClear() = 0; 1772254SN/A virtual void profileSample() = 0; 1782235SN/A#endif 1792235SN/A 1802190SN/A virtual int getThreadNum() = 0; 1812159SN/A 1822235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1832254SN/A // However, may be quite useful in SPARC. 1842190SN/A virtual TheISA::MachInst getInst() = 0; 1852159SN/A 1862680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1872159SN/A 1882190SN/A virtual void clearArchRegs() = 0; 1892159SN/A 1902159SN/A // 1912159SN/A // New accessors for new decoder. 1922159SN/A // 1932190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1942159SN/A 1952455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1962159SN/A 1972455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1982159SN/A 1992455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 2002455SN/A 2012455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2022159SN/A 2032190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2042159SN/A 2052455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2062159SN/A 2072455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2082159SN/A 2092455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2102455SN/A 2112455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2122159SN/A 2132190SN/A virtual uint64_t readPC() = 0; 2142159SN/A 2152190SN/A virtual void setPC(uint64_t val) = 0; 2162159SN/A 2172190SN/A virtual uint64_t readNextPC() = 0; 2182159SN/A 2192190SN/A virtual void setNextPC(uint64_t val) = 0; 2202159SN/A 2212447SN/A virtual uint64_t readNextNPC() = 0; 2222447SN/A 2232447SN/A virtual void setNextNPC(uint64_t val) = 0; 2242447SN/A 2252190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2262159SN/A 2272190SN/A virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 2282190SN/A 2292190SN/A virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 2302190SN/A 2312190SN/A virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 2322190SN/A 2332235SN/A // Also not necessarily the best location for these two. Hopefully will go 2342235SN/A // away once we decide upon where st cond failures goes. 2352190SN/A virtual unsigned readStCondFailures() = 0; 2362190SN/A 2372190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2382159SN/A 2392159SN/A#if FULL_SYSTEM 2402190SN/A virtual bool inPalMode() = 0; 2412159SN/A#endif 2422159SN/A 2432235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2442190SN/A virtual bool misspeculating() = 0; 2452190SN/A 2462159SN/A#if !FULL_SYSTEM 2472190SN/A virtual IntReg getSyscallArg(int i) = 0; 2482159SN/A 2492159SN/A // used to shift args for indirect syscall 2502190SN/A virtual void setSyscallArg(int i, IntReg val) = 0; 2512159SN/A 2522190SN/A virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2532159SN/A 2542235SN/A // Same with st cond failures. 2552190SN/A virtual Counter readFuncExeInst() = 0; 2562834Sksewell@umich.edu 2572834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2582834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2592834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2602834Sksewell@umich.edu virtual int exit() { return 1; }; 2612159SN/A#endif 2622525SN/A 2632972Sgblack@eecs.umich.edu virtual void changeRegFileContext(TheISA::RegContextParam param, 2642972Sgblack@eecs.umich.edu TheISA::RegContextVal val) = 0; 2652159SN/A}; 2662159SN/A 2672682Sktlim@umich.edu/** 2682682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2692682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2702682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2712682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2722682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2732682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2742682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2752682Sktlim@umich.edu * simple_thread.hh for an example of this. 2762682Sktlim@umich.edu */ 2772680Sktlim@umich.edutemplate <class TC> 2782680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2792190SN/A{ 2802190SN/A public: 2812680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2822680Sktlim@umich.edu { actualTC = actual_tc; } 2832159SN/A 2842190SN/A private: 2852680Sktlim@umich.edu TC *actualTC; 2862SN/A 2872SN/A public: 2882SN/A 2892680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2902SN/A 2912680Sktlim@umich.edu void setCpuId(int id) { actualTC->setCpuId(id); } 292716SN/A 2932680Sktlim@umich.edu int readCpuId() { return actualTC->readCpuId(); } 2942SN/A 2951858SN/A#if FULL_SYSTEM 2962680Sktlim@umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2972SN/A 2983453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 2991917SN/A 3003453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 3012521SN/A 3022680Sktlim@umich.edu Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 3032654SN/A 3042680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3052521SN/A 3062680Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 3072521SN/A 3082680Sktlim@umich.edu void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 3092SN/A#else 3102680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3112518SN/A 3122680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3132SN/A#endif 3142SN/A 3152680Sktlim@umich.edu Status status() const { return actualTC->status(); } 316595SN/A 3172680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3182SN/A 3192190SN/A /// Set the status to Active. Optional delay indicates number of 3202190SN/A /// cycles to wait before beginning execution. 3212680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3222SN/A 3232190SN/A /// Set the status to Suspended. 3242680Sktlim@umich.edu void suspend() { actualTC->suspend(); } 3252SN/A 3262190SN/A /// Set the status to Unallocated. 3272875Sksewell@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(); } 3282SN/A 3292190SN/A /// Set the status to Halted. 3302680Sktlim@umich.edu void halt() { actualTC->halt(); } 331217SN/A 3321858SN/A#if FULL_SYSTEM 3332680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3342190SN/A#endif 3352190SN/A 3362680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3372680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3382190SN/A 3392680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3402190SN/A 3412680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3422190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3432680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3442190SN/A 3452235SN/A#if FULL_SYSTEM 3462680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3472235SN/A 3482680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3492680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3502254SN/A 3512680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3522680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3532235SN/A#endif 3542235SN/A 3552680Sktlim@umich.edu int getThreadNum() { return actualTC->getThreadNum(); } 3562190SN/A 3572190SN/A // @todo: Do I need this? 3582680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3592SN/A 3602190SN/A // @todo: Do I need this? 3612680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3622SN/A 3632680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 364716SN/A 3652SN/A // 3662SN/A // New accessors for new decoder. 3672SN/A // 3682SN/A uint64_t readIntReg(int reg_idx) 3692680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3702SN/A 3712455SN/A FloatReg readFloatReg(int reg_idx, int width) 3722680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3732SN/A 3742455SN/A FloatReg readFloatReg(int reg_idx) 3752680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3762SN/A 3772455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3782680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3792455SN/A 3802455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3812680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3822SN/A 3832SN/A void setIntReg(int reg_idx, uint64_t val) 3842680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3852SN/A 3862455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3872680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3882SN/A 3892455SN/A void setFloatReg(int reg_idx, FloatReg val) 3902680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3912SN/A 3922455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 3932680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 3942455SN/A 3952455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3962680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3972SN/A 3982680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 3992SN/A 4002680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 4012206SN/A 4022680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4032252SN/A 4042680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4052SN/A 4062680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4072447SN/A 4082680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4092447SN/A 4102159SN/A MiscReg readMiscReg(int misc_reg) 4112680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4122SN/A 4132159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 4142680Sktlim@umich.edu { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 4152SN/A 4162159SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 4172680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4182SN/A 4192159SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 4202680Sktlim@umich.edu { return actualTC->setMiscRegWithEffect(misc_reg, val); } 4212190SN/A 4222190SN/A unsigned readStCondFailures() 4232680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4242190SN/A 4252190SN/A void setStCondFailures(unsigned sc_failures) 4262680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4271858SN/A#if FULL_SYSTEM 4282680Sktlim@umich.edu bool inPalMode() { return actualTC->inPalMode(); } 4292SN/A#endif 4302SN/A 4312190SN/A // @todo: Fix this! 4322680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4332190SN/A 4341858SN/A#if !FULL_SYSTEM 4352680Sktlim@umich.edu IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 436360SN/A 437360SN/A // used to shift args for indirect syscall 4382190SN/A void setSyscallArg(int i, IntReg val) 4392680Sktlim@umich.edu { actualTC->setSyscallArg(i, val); } 440360SN/A 4411450SN/A void setSyscallReturn(SyscallReturn return_value) 4422680Sktlim@umich.edu { actualTC->setSyscallReturn(return_value); } 443360SN/A 4442680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4452SN/A#endif 4462525SN/A 4472972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4482972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4492525SN/A { 4502680Sktlim@umich.edu actualTC->changeRegFileContext(param, val); 4512525SN/A } 4522SN/A}; 4532SN/A 4542190SN/A#endif 455