thread_context.hh revision 2518 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_EXEC_CONTEXT_HH__
30#define __CPU_EXEC_CONTEXT_HH__
31
32#include "config/full_system.hh"
33#include "mem/request.hh"
34#include "sim/faults.hh"
35#include "sim/host.hh"
36#include "sim/serialize.hh"
37#include "sim/byteswap.hh"
38
39// @todo: Figure out a more architecture independent way to obtain the ITB and
40// DTB pointers.
41class AlphaDTB;
42class AlphaITB;
43class BaseCPU;
44class Event;
45class TranslatingPort;
46class Process;
47class System;
48
49class ExecContext
50{
51  protected:
52    typedef TheISA::RegFile RegFile;
53    typedef TheISA::MachInst MachInst;
54    typedef TheISA::IntReg IntReg;
55    typedef TheISA::FloatReg FloatReg;
56    typedef TheISA::FloatRegBits FloatRegBits;
57    typedef TheISA::MiscRegFile MiscRegFile;
58    typedef TheISA::MiscReg MiscReg;
59  public:
60    enum Status
61    {
62        /// Initialized but not running yet.  All CPUs start in
63        /// this state, but most transition to Active on cycle 1.
64        /// In MP or SMT systems, non-primary contexts will stay
65        /// in this state until a thread is assigned to them.
66        Unallocated,
67
68        /// Running.  Instructions should be executed only when
69        /// the context is in this state.
70        Active,
71
72        /// Temporarily inactive.  Entered while waiting for
73        /// synchronization, etc.
74        Suspended,
75
76        /// Permanently shut down.  Entered when target executes
77        /// m5exit pseudo-instruction.  When all contexts enter
78        /// this state, the simulation will terminate.
79        Halted
80    };
81
82    virtual ~ExecContext() { };
83
84    virtual BaseCPU *getCpuPtr() = 0;
85
86    virtual void setCpuId(int id) = 0;
87
88    virtual int readCpuId() = 0;
89
90#if FULL_SYSTEM
91    virtual System *getSystemPtr() = 0;
92
93    virtual AlphaITB *getITBPtr() = 0;
94
95    virtual AlphaDTB * getDTBPtr() = 0;
96#else
97    virtual TranslatingPort *getMemPort() = 0;
98
99    virtual Process *getProcessPtr() = 0;
100#endif
101
102    virtual Status status() const = 0;
103
104    virtual void setStatus(Status new_status) = 0;
105
106    /// Set the status to Active.  Optional delay indicates number of
107    /// cycles to wait before beginning execution.
108    virtual void activate(int delay = 1) = 0;
109
110    /// Set the status to Suspended.
111    virtual void suspend() = 0;
112
113    /// Set the status to Unallocated.
114    virtual void deallocate() = 0;
115
116    /// Set the status to Halted.
117    virtual void halt() = 0;
118
119#if FULL_SYSTEM
120    virtual void dumpFuncProfile() = 0;
121#endif
122
123    virtual void takeOverFrom(ExecContext *old_context) = 0;
124
125    virtual void regStats(const std::string &name) = 0;
126
127    virtual void serialize(std::ostream &os) = 0;
128    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
129
130#if FULL_SYSTEM
131    virtual Event *getQuiesceEvent() = 0;
132
133    // Not necessarily the best location for these...
134    // Having an extra function just to read these is obnoxious
135    virtual Tick readLastActivate() = 0;
136    virtual Tick readLastSuspend() = 0;
137
138    virtual void profileClear() = 0;
139    virtual void profileSample() = 0;
140#endif
141
142    virtual int getThreadNum() = 0;
143
144    virtual int getInstAsid() = 0;
145    virtual int getDataAsid() = 0;
146
147    virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
148
149    virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
150
151    virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
152
153    // Also somewhat obnoxious.  Really only used for the TLB fault.
154    // However, may be quite useful in SPARC.
155    virtual TheISA::MachInst getInst() = 0;
156
157    virtual void copyArchRegs(ExecContext *xc) = 0;
158
159    virtual void clearArchRegs() = 0;
160
161    //
162    // New accessors for new decoder.
163    //
164    virtual uint64_t readIntReg(int reg_idx) = 0;
165
166    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
167
168    virtual FloatReg readFloatReg(int reg_idx) = 0;
169
170    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
171
172    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
173
174    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
175
176    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
177
178    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
179
180    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
181
182    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
183
184    virtual uint64_t readPC() = 0;
185
186    virtual void setPC(uint64_t val) = 0;
187
188    virtual uint64_t readNextPC() = 0;
189
190    virtual void setNextPC(uint64_t val) = 0;
191
192    virtual uint64_t readNextNPC() = 0;
193
194    virtual void setNextNPC(uint64_t val) = 0;
195
196    virtual MiscReg readMiscReg(int misc_reg) = 0;
197
198    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
199
200    virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
201
202    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
203
204    // Also not necessarily the best location for these two.  Hopefully will go
205    // away once we decide upon where st cond failures goes.
206    virtual unsigned readStCondFailures() = 0;
207
208    virtual void setStCondFailures(unsigned sc_failures) = 0;
209
210#if FULL_SYSTEM
211    virtual int readIntrFlag() = 0;
212    virtual void setIntrFlag(int val) = 0;
213    virtual Fault hwrei() = 0;
214    virtual bool inPalMode() = 0;
215    virtual bool simPalCheck(int palFunc) = 0;
216#endif
217
218    // Only really makes sense for old CPU model.  Still could be useful though.
219    virtual bool misspeculating() = 0;
220
221#if !FULL_SYSTEM
222    virtual IntReg getSyscallArg(int i) = 0;
223
224    // used to shift args for indirect syscall
225    virtual void setSyscallArg(int i, IntReg val) = 0;
226
227    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
228
229    virtual void syscall() = 0;
230
231    // Same with st cond failures.
232    virtual Counter readFuncExeInst() = 0;
233
234    virtual void setFuncExeInst(Counter new_val) = 0;
235#endif
236};
237
238template <class XC>
239class ProxyExecContext : public ExecContext
240{
241  public:
242    ProxyExecContext(XC *actual_xc)
243    { actualXC = actual_xc; }
244
245  private:
246    XC *actualXC;
247
248  public:
249
250    BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
251
252    void setCpuId(int id) { actualXC->setCpuId(id); }
253
254    int readCpuId() { return actualXC->readCpuId(); }
255
256#if FULL_SYSTEM
257    System *getSystemPtr() { return actualXC->getSystemPtr(); }
258
259    AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
260
261    AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
262#else
263    TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
264
265    Process *getProcessPtr() { return actualXC->getProcessPtr(); }
266#endif
267
268    Status status() const { return actualXC->status(); }
269
270    void setStatus(Status new_status) { actualXC->setStatus(new_status); }
271
272    /// Set the status to Active.  Optional delay indicates number of
273    /// cycles to wait before beginning execution.
274    void activate(int delay = 1) { actualXC->activate(delay); }
275
276    /// Set the status to Suspended.
277    void suspend() { actualXC->suspend(); }
278
279    /// Set the status to Unallocated.
280    void deallocate() { actualXC->deallocate(); }
281
282    /// Set the status to Halted.
283    void halt() { actualXC->halt(); }
284
285#if FULL_SYSTEM
286    void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
287#endif
288
289    void takeOverFrom(ExecContext *oldContext)
290    { actualXC->takeOverFrom(oldContext); }
291
292    void regStats(const std::string &name) { actualXC->regStats(name); }
293
294    void serialize(std::ostream &os) { actualXC->serialize(os); }
295    void unserialize(Checkpoint *cp, const std::string &section)
296    { actualXC->unserialize(cp, section); }
297
298#if FULL_SYSTEM
299    Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
300
301    Tick readLastActivate() { return actualXC->readLastActivate(); }
302    Tick readLastSuspend() { return actualXC->readLastSuspend(); }
303
304    void profileClear() { return actualXC->profileClear(); }
305    void profileSample() { return actualXC->profileSample(); }
306#endif
307
308    int getThreadNum() { return actualXC->getThreadNum(); }
309
310    int getInstAsid() { return actualXC->getInstAsid(); }
311    int getDataAsid() { return actualXC->getDataAsid(); }
312
313    Fault translateInstReq(CpuRequestPtr &req)
314    { return actualXC->translateInstReq(req); }
315
316    Fault translateDataReadReq(CpuRequestPtr &req)
317    { return actualXC->translateDataReadReq(req); }
318
319    Fault translateDataWriteReq(CpuRequestPtr &req)
320    { return actualXC->translateDataWriteReq(req); }
321
322    // @todo: Do I need this?
323    MachInst getInst() { return actualXC->getInst(); }
324
325    // @todo: Do I need this?
326    void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
327
328    void clearArchRegs() { actualXC->clearArchRegs(); }
329
330    //
331    // New accessors for new decoder.
332    //
333    uint64_t readIntReg(int reg_idx)
334    { return actualXC->readIntReg(reg_idx); }
335
336    FloatReg readFloatReg(int reg_idx, int width)
337    { return actualXC->readFloatReg(reg_idx, width); }
338
339    FloatReg readFloatReg(int reg_idx)
340    { return actualXC->readFloatReg(reg_idx); }
341
342    FloatRegBits readFloatRegBits(int reg_idx, int width)
343    { return actualXC->readFloatRegBits(reg_idx, width); }
344
345    FloatRegBits readFloatRegBits(int reg_idx)
346    { return actualXC->readFloatRegBits(reg_idx); }
347
348    void setIntReg(int reg_idx, uint64_t val)
349    { actualXC->setIntReg(reg_idx, val); }
350
351    void setFloatReg(int reg_idx, FloatReg val, int width)
352    { actualXC->setFloatReg(reg_idx, val, width); }
353
354    void setFloatReg(int reg_idx, FloatReg val)
355    { actualXC->setFloatReg(reg_idx, val); }
356
357    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
358    { actualXC->setFloatRegBits(reg_idx, val, width); }
359
360    void setFloatRegBits(int reg_idx, FloatRegBits val)
361    { actualXC->setFloatRegBits(reg_idx, val); }
362
363    uint64_t readPC() { return actualXC->readPC(); }
364
365    void setPC(uint64_t val) { actualXC->setPC(val); }
366
367    uint64_t readNextPC() { return actualXC->readNextPC(); }
368
369    void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
370
371    uint64_t readNextNPC() { return actualXC->readNextNPC(); }
372
373    void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
374
375    MiscReg readMiscReg(int misc_reg)
376    { return actualXC->readMiscReg(misc_reg); }
377
378    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
379    { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
380
381    Fault setMiscReg(int misc_reg, const MiscReg &val)
382    { return actualXC->setMiscReg(misc_reg, val); }
383
384    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
385    { return actualXC->setMiscRegWithEffect(misc_reg, val); }
386
387    unsigned readStCondFailures()
388    { return actualXC->readStCondFailures(); }
389
390    void setStCondFailures(unsigned sc_failures)
391    { actualXC->setStCondFailures(sc_failures); }
392
393#if FULL_SYSTEM
394    int readIntrFlag() { return actualXC->readIntrFlag(); }
395
396    void setIntrFlag(int val) { actualXC->setIntrFlag(val); }
397
398    Fault hwrei() { return actualXC->hwrei(); }
399
400    bool inPalMode() { return actualXC->inPalMode(); }
401
402    bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
403#endif
404
405    // @todo: Fix this!
406    bool misspeculating() { return actualXC->misspeculating(); }
407
408#if !FULL_SYSTEM
409    IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
410
411    // used to shift args for indirect syscall
412    void setSyscallArg(int i, IntReg val)
413    { actualXC->setSyscallArg(i, val); }
414
415    void setSyscallReturn(SyscallReturn return_value)
416    { actualXC->setSyscallReturn(return_value); }
417
418    void syscall() { actualXC->syscall(); }
419
420    Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
421
422    void setFuncExeInst(Counter new_val)
423    { return actualXC->setFuncExeInst(new_val); }
424#endif
425};
426
427#endif
428