thread_context.hh revision 2455
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/request.hh" 34#include "sim/faults.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "sim/byteswap.hh" 38 39// forward declaration: see functional_memory.hh 40// @todo: Figure out a more architecture independent way to obtain the ITB and 41// DTB pointers. 42class AlphaDTB; 43class AlphaITB; 44class BaseCPU; 45class Event; 46class PhysicalMemory; 47class TranslatingPort; 48class Process; 49class System; 50 51class ExecContext 52{ 53 protected: 54 typedef TheISA::RegFile RegFile; 55 typedef TheISA::MachInst MachInst; 56 typedef TheISA::IntReg IntReg; 57 typedef TheISA::FloatReg FloatReg; 58 typedef TheISA::FloatRegBits FloatRegBits; 59 typedef TheISA::MiscRegFile MiscRegFile; 60 typedef TheISA::MiscReg MiscReg; 61 public: 62 enum Status 63 { 64 /// Initialized but not running yet. All CPUs start in 65 /// this state, but most transition to Active on cycle 1. 66 /// In MP or SMT systems, non-primary contexts will stay 67 /// in this state until a thread is assigned to them. 68 Unallocated, 69 70 /// Running. Instructions should be executed only when 71 /// the context is in this state. 72 Active, 73 74 /// Temporarily inactive. Entered while waiting for 75 /// synchronization, etc. 76 Suspended, 77 78 /// Permanently shut down. Entered when target executes 79 /// m5exit pseudo-instruction. When all contexts enter 80 /// this state, the simulation will terminate. 81 Halted 82 }; 83 84 virtual ~ExecContext() { }; 85 86 virtual TranslatingPort *getMemPort() = 0; 87 88 virtual BaseCPU *getCpuPtr() = 0; 89 90 virtual void setCpuId(int id) = 0; 91 92 virtual int readCpuId() = 0; 93 94#if FULL_SYSTEM 95 virtual System *getSystemPtr() = 0; 96 97 virtual PhysicalMemory *getPhysMemPtr() = 0; 98 99 virtual AlphaITB *getITBPtr() = 0; 100 101 virtual AlphaDTB * getDTBPtr() = 0; 102#else 103 virtual Process *getProcessPtr() = 0; 104#endif 105 106 virtual Status status() const = 0; 107 108 virtual void setStatus(Status new_status) = 0; 109 110 /// Set the status to Active. Optional delay indicates number of 111 /// cycles to wait before beginning execution. 112 virtual void activate(int delay = 1) = 0; 113 114 /// Set the status to Suspended. 115 virtual void suspend() = 0; 116 117 /// Set the status to Unallocated. 118 virtual void deallocate() = 0; 119 120 /// Set the status to Halted. 121 virtual void halt() = 0; 122 123#if FULL_SYSTEM 124 virtual void dumpFuncProfile() = 0; 125#endif 126 127 virtual void takeOverFrom(ExecContext *old_context) = 0; 128 129 virtual void regStats(const std::string &name) = 0; 130 131 virtual void serialize(std::ostream &os) = 0; 132 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 133 134#if FULL_SYSTEM 135 virtual Event *getQuiesceEvent() = 0; 136 137 // Not necessarily the best location for these... 138 // Having an extra function just to read these is obnoxious 139 virtual Tick readLastActivate() = 0; 140 virtual Tick readLastSuspend() = 0; 141 142 virtual void profileClear() = 0; 143 virtual void profileSample() = 0; 144#endif 145 146 virtual int getThreadNum() = 0; 147 148 virtual int getInstAsid() = 0; 149 virtual int getDataAsid() = 0; 150 151 virtual Fault translateInstReq(CpuRequestPtr &req) = 0; 152 153 virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0; 154 155 virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0; 156 157 // Also somewhat obnoxious. Really only used for the TLB fault. 158 // However, may be quite useful in SPARC. 159 virtual TheISA::MachInst getInst() = 0; 160 161 virtual void copyArchRegs(ExecContext *xc) = 0; 162 163 virtual void clearArchRegs() = 0; 164 165 // 166 // New accessors for new decoder. 167 // 168 virtual uint64_t readIntReg(int reg_idx) = 0; 169 170 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 171 172 virtual FloatReg readFloatReg(int reg_idx) = 0; 173 174 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 175 176 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 177 178 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 179 180 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 181 182 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 183 184 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 185 186 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 187 188 virtual uint64_t readPC() = 0; 189 190 virtual void setPC(uint64_t val) = 0; 191 192 virtual uint64_t readNextPC() = 0; 193 194 virtual void setNextPC(uint64_t val) = 0; 195 196 virtual uint64_t readNextNPC() = 0; 197 198 virtual void setNextNPC(uint64_t val) = 0; 199 200 virtual MiscReg readMiscReg(int misc_reg) = 0; 201 202 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 203 204 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 205 206 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 207 208 // Also not necessarily the best location for these two. Hopefully will go 209 // away once we decide upon where st cond failures goes. 210 virtual unsigned readStCondFailures() = 0; 211 212 virtual void setStCondFailures(unsigned sc_failures) = 0; 213 214#if FULL_SYSTEM 215 virtual int readIntrFlag() = 0; 216 virtual void setIntrFlag(int val) = 0; 217 virtual Fault hwrei() = 0; 218 virtual bool inPalMode() = 0; 219 virtual bool simPalCheck(int palFunc) = 0; 220#endif 221 222 // Only really makes sense for old CPU model. Still could be useful though. 223 virtual bool misspeculating() = 0; 224 225#if !FULL_SYSTEM 226 virtual IntReg getSyscallArg(int i) = 0; 227 228 // used to shift args for indirect syscall 229 virtual void setSyscallArg(int i, IntReg val) = 0; 230 231 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 232 233 virtual void syscall() = 0; 234 235 // Same with st cond failures. 236 virtual Counter readFuncExeInst() = 0; 237 238 virtual void setFuncExeInst(Counter new_val) = 0; 239#endif 240}; 241 242template <class XC> 243class ProxyExecContext : public ExecContext 244{ 245 public: 246 ProxyExecContext(XC *actual_xc) 247 { actualXC = actual_xc; } 248 249 private: 250 XC *actualXC; 251 252 public: 253 254 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 255 256 BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } 257 258 void setCpuId(int id) { actualXC->setCpuId(id); } 259 260 int readCpuId() { return actualXC->readCpuId(); } 261 262#if FULL_SYSTEM 263 System *getSystemPtr() { return actualXC->getSystemPtr(); } 264 265 PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); } 266 267 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 268 269 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 270#else 271 Process *getProcessPtr() { return actualXC->getProcessPtr(); } 272#endif 273 274 Status status() const { return actualXC->status(); } 275 276 void setStatus(Status new_status) { actualXC->setStatus(new_status); } 277 278 /// Set the status to Active. Optional delay indicates number of 279 /// cycles to wait before beginning execution. 280 void activate(int delay = 1) { actualXC->activate(delay); } 281 282 /// Set the status to Suspended. 283 void suspend() { actualXC->suspend(); } 284 285 /// Set the status to Unallocated. 286 void deallocate() { actualXC->deallocate(); } 287 288 /// Set the status to Halted. 289 void halt() { actualXC->halt(); } 290 291#if FULL_SYSTEM 292 void dumpFuncProfile() { actualXC->dumpFuncProfile(); } 293#endif 294 295 void takeOverFrom(ExecContext *oldContext) 296 { actualXC->takeOverFrom(oldContext); } 297 298 void regStats(const std::string &name) { actualXC->regStats(name); } 299 300 void serialize(std::ostream &os) { actualXC->serialize(os); } 301 void unserialize(Checkpoint *cp, const std::string §ion) 302 { actualXC->unserialize(cp, section); } 303 304#if FULL_SYSTEM 305 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } 306 307 Tick readLastActivate() { return actualXC->readLastActivate(); } 308 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 309 310 void profileClear() { return actualXC->profileClear(); } 311 void profileSample() { return actualXC->profileSample(); } 312#endif 313 314 int getThreadNum() { return actualXC->getThreadNum(); } 315 316 int getInstAsid() { return actualXC->getInstAsid(); } 317 int getDataAsid() { return actualXC->getDataAsid(); } 318 319 Fault translateInstReq(CpuRequestPtr &req) 320 { return actualXC->translateInstReq(req); } 321 322 Fault translateDataReadReq(CpuRequestPtr &req) 323 { return actualXC->translateDataReadReq(req); } 324 325 Fault translateDataWriteReq(CpuRequestPtr &req) 326 { return actualXC->translateDataWriteReq(req); } 327 328 // @todo: Do I need this? 329 MachInst getInst() { return actualXC->getInst(); } 330 331 // @todo: Do I need this? 332 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 333 334 void clearArchRegs() { actualXC->clearArchRegs(); } 335 336 // 337 // New accessors for new decoder. 338 // 339 uint64_t readIntReg(int reg_idx) 340 { return actualXC->readIntReg(reg_idx); } 341 342 FloatReg readFloatReg(int reg_idx, int width) 343 { return actualXC->readFloatReg(reg_idx, width); } 344 345 FloatReg readFloatReg(int reg_idx) 346 { return actualXC->readFloatReg(reg_idx); } 347 348 FloatRegBits readFloatRegBits(int reg_idx, int width) 349 { return actualXC->readFloatRegBits(reg_idx, width); } 350 351 FloatRegBits readFloatRegBits(int reg_idx) 352 { return actualXC->readFloatRegBits(reg_idx); } 353 354 void setIntReg(int reg_idx, uint64_t val) 355 { actualXC->setIntReg(reg_idx, val); } 356 357 void setFloatReg(int reg_idx, FloatReg val, int width) 358 { actualXC->setFloatReg(reg_idx, val, width); } 359 360 void setFloatReg(int reg_idx, FloatReg val) 361 { actualXC->setFloatReg(reg_idx, val); } 362 363 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 364 { actualXC->setFloatRegBits(reg_idx, val, width); } 365 366 void setFloatRegBits(int reg_idx, FloatRegBits val) 367 { actualXC->setFloatRegBits(reg_idx, val); } 368 369 uint64_t readPC() { return actualXC->readPC(); } 370 371 void setPC(uint64_t val) { actualXC->setPC(val); } 372 373 uint64_t readNextPC() { return actualXC->readNextPC(); } 374 375 void setNextPC(uint64_t val) { actualXC->setNextPC(val); } 376 377 uint64_t readNextNPC() { return actualXC->readNextNPC(); } 378 379 void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); } 380 381 MiscReg readMiscReg(int misc_reg) 382 { return actualXC->readMiscReg(misc_reg); } 383 384 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 385 { return actualXC->readMiscRegWithEffect(misc_reg, fault); } 386 387 Fault setMiscReg(int misc_reg, const MiscReg &val) 388 { return actualXC->setMiscReg(misc_reg, val); } 389 390 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 391 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 392 393 unsigned readStCondFailures() 394 { return actualXC->readStCondFailures(); } 395 396 void setStCondFailures(unsigned sc_failures) 397 { actualXC->setStCondFailures(sc_failures); } 398 399#if FULL_SYSTEM 400 int readIntrFlag() { return actualXC->readIntrFlag(); } 401 402 void setIntrFlag(int val) { actualXC->setIntrFlag(val); } 403 404 Fault hwrei() { return actualXC->hwrei(); } 405 406 bool inPalMode() { return actualXC->inPalMode(); } 407 408 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); } 409#endif 410 411 // @todo: Fix this! 412 bool misspeculating() { return actualXC->misspeculating(); } 413 414#if !FULL_SYSTEM 415 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 416 417 // used to shift args for indirect syscall 418 void setSyscallArg(int i, IntReg val) 419 { actualXC->setSyscallArg(i, val); } 420 421 void setSyscallReturn(SyscallReturn return_value) 422 { actualXC->setSyscallReturn(return_value); } 423 424 void syscall() { actualXC->syscall(); } 425 426 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } 427 428 void setFuncExeInst(Counter new_val) 429 { return actualXC->setFuncExeInst(new_val); } 430#endif 431}; 432 433#endif 434