thread_context.hh revision 2254 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_EXEC_CONTEXT_HH__
30#define __CPU_EXEC_CONTEXT_HH__
31
32#include "config/full_system.hh"
33#include "mem/mem_req.hh"
34#include "sim/faults.hh"
35#include "sim/host.hh"
36#include "sim/serialize.hh"
37#include "sim/byteswap.hh"
38
39// forward declaration: see functional_memory.hh
40// @todo: Figure out a more architecture independent way to obtain the ITB and
41// DTB pointers.
42class AlphaDTB;
43class AlphaITB;
44class BaseCPU;
45class Event;
46class FunctionalMemory;
47class PhysicalMemory;
48class Process;
49class System;
50
51class ExecContext
52{
53  protected:
54    typedef TheISA::RegFile RegFile;
55    typedef TheISA::MachInst MachInst;
56    typedef TheISA::IntReg IntReg;
57    typedef TheISA::MiscRegFile MiscRegFile;
58    typedef TheISA::MiscReg MiscReg;
59  public:
60    enum Status
61    {
62        /// Initialized but not running yet.  All CPUs start in
63        /// this state, but most transition to Active on cycle 1.
64        /// In MP or SMT systems, non-primary contexts will stay
65        /// in this state until a thread is assigned to them.
66        Unallocated,
67
68        /// Running.  Instructions should be executed only when
69        /// the context is in this state.
70        Active,
71
72        /// Temporarily inactive.  Entered while waiting for
73        /// synchronization, etc.
74        Suspended,
75
76        /// Permanently shut down.  Entered when target executes
77        /// m5exit pseudo-instruction.  When all contexts enter
78        /// this state, the simulation will terminate.
79        Halted
80    };
81
82    virtual ~ExecContext() { };
83
84    virtual BaseCPU *getCpuPtr() = 0;
85
86    virtual void setCpuId(int id) = 0;
87
88    virtual int readCpuId() = 0;
89
90    virtual FunctionalMemory *getMemPtr() = 0;
91
92#if FULL_SYSTEM
93    virtual System *getSystemPtr() = 0;
94
95    virtual PhysicalMemory *getPhysMemPtr() = 0;
96
97    virtual AlphaITB *getITBPtr() = 0;
98
99    virtual AlphaDTB * getDTBPtr() = 0;
100#else
101    virtual Process *getProcessPtr() = 0;
102#endif
103
104    virtual Status status() const = 0;
105
106    virtual void setStatus(Status new_status) = 0;
107
108    /// Set the status to Active.  Optional delay indicates number of
109    /// cycles to wait before beginning execution.
110    virtual void activate(int delay = 1) = 0;
111
112    /// Set the status to Suspended.
113    virtual void suspend() = 0;
114
115    /// Set the status to Unallocated.
116    virtual void deallocate() = 0;
117
118    /// Set the status to Halted.
119    virtual void halt() = 0;
120
121#if FULL_SYSTEM
122    virtual void dumpFuncProfile() = 0;
123#endif
124
125    virtual void takeOverFrom(ExecContext *old_context) = 0;
126
127    virtual void regStats(const std::string &name) = 0;
128
129    virtual void serialize(std::ostream &os) = 0;
130    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
131
132#if FULL_SYSTEM
133    virtual Event *getQuiesceEvent() = 0;
134
135    // Not necessarily the best location for these...
136    // Having an extra function just to read these is obnoxious
137    virtual Tick readLastActivate() = 0;
138    virtual Tick readLastSuspend() = 0;
139
140    virtual void profileClear() = 0;
141    virtual void profileSample() = 0;
142#endif
143
144    virtual int getThreadNum() = 0;
145
146    virtual bool validInstAddr(Addr addr) = 0;
147    virtual bool validDataAddr(Addr addr) = 0;
148    virtual int getInstAsid() = 0;
149    virtual int getDataAsid() = 0;
150
151    virtual Fault translateInstReq(MemReqPtr &req) = 0;
152
153    virtual Fault translateDataReadReq(MemReqPtr &req) = 0;
154
155    virtual Fault translateDataWriteReq(MemReqPtr &req) = 0;
156
157    // Also somewhat obnoxious.  Really only used for the TLB fault.
158    // However, may be quite useful in SPARC.
159    virtual TheISA::MachInst getInst() = 0;
160
161    virtual void copyArchRegs(ExecContext *xc) = 0;
162
163    virtual void clearArchRegs() = 0;
164
165    //
166    // New accessors for new decoder.
167    //
168    virtual uint64_t readIntReg(int reg_idx) = 0;
169
170    virtual float readFloatRegSingle(int reg_idx) = 0;
171
172    virtual double readFloatRegDouble(int reg_idx) = 0;
173
174    virtual uint64_t readFloatRegInt(int reg_idx) = 0;
175
176    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
177
178    virtual void setFloatRegSingle(int reg_idx, float val) = 0;
179
180    virtual void setFloatRegDouble(int reg_idx, double val) = 0;
181
182    virtual void setFloatRegInt(int reg_idx, uint64_t val) = 0;
183
184    virtual uint64_t readPC() = 0;
185
186    virtual void setPC(uint64_t val) = 0;
187
188    virtual uint64_t readNextPC() = 0;
189
190    virtual void setNextPC(uint64_t val) = 0;
191
192    virtual MiscReg readMiscReg(int misc_reg) = 0;
193
194    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
195
196    virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
197
198    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
199
200    // Also not necessarily the best location for these two.  Hopefully will go
201    // away once we decide upon where st cond failures goes.
202    virtual unsigned readStCondFailures() = 0;
203
204    virtual void setStCondFailures(unsigned sc_failures) = 0;
205
206#if FULL_SYSTEM
207    virtual int readIntrFlag() = 0;
208    virtual void setIntrFlag(int val) = 0;
209    virtual Fault hwrei() = 0;
210    virtual bool inPalMode() = 0;
211    virtual bool simPalCheck(int palFunc) = 0;
212#endif
213
214    // Only really makes sense for old CPU model.  Still could be useful though.
215    virtual bool misspeculating() = 0;
216
217#if !FULL_SYSTEM
218    virtual IntReg getSyscallArg(int i) = 0;
219
220    // used to shift args for indirect syscall
221    virtual void setSyscallArg(int i, IntReg val) = 0;
222
223    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
224
225    virtual void syscall() = 0;
226
227    // Same with st cond failures.
228    virtual Counter readFuncExeInst() = 0;
229
230    virtual void setFuncExeInst(Counter new_val) = 0;
231#endif
232};
233
234template <class XC>
235class ProxyExecContext : public ExecContext
236{
237  public:
238    ProxyExecContext(XC *actual_xc)
239    { actualXC = actual_xc; }
240
241  private:
242    XC *actualXC;
243
244  public:
245
246    BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
247
248    void setCpuId(int id) { actualXC->setCpuId(id); }
249
250    int readCpuId() { return actualXC->readCpuId(); }
251
252    FunctionalMemory *getMemPtr() { return actualXC->getMemPtr(); }
253
254#if FULL_SYSTEM
255    System *getSystemPtr() { return actualXC->getSystemPtr(); }
256
257    PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
258
259    AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
260
261    AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
262#else
263    Process *getProcessPtr() { return actualXC->getProcessPtr(); }
264#endif
265
266    Status status() const { return actualXC->status(); }
267
268    void setStatus(Status new_status) { actualXC->setStatus(new_status); }
269
270    /// Set the status to Active.  Optional delay indicates number of
271    /// cycles to wait before beginning execution.
272    void activate(int delay = 1) { actualXC->activate(delay); }
273
274    /// Set the status to Suspended.
275    void suspend() { actualXC->suspend(); }
276
277    /// Set the status to Unallocated.
278    void deallocate() { actualXC->deallocate(); }
279
280    /// Set the status to Halted.
281    void halt() { actualXC->halt(); }
282
283#if FULL_SYSTEM
284    void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
285#endif
286
287    void takeOverFrom(ExecContext *oldContext)
288    { actualXC->takeOverFrom(oldContext); }
289
290    void regStats(const std::string &name) { actualXC->regStats(name); }
291
292    void serialize(std::ostream &os) { actualXC->serialize(os); }
293    void unserialize(Checkpoint *cp, const std::string &section)
294    { actualXC->unserialize(cp, section); }
295
296#if FULL_SYSTEM
297    Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
298
299    Tick readLastActivate() { return actualXC->readLastActivate(); }
300    Tick readLastSuspend() { return actualXC->readLastSuspend(); }
301
302    void profileClear() { return actualXC->profileClear(); }
303    void profileSample() { return actualXC->profileSample(); }
304#endif
305
306    int getThreadNum() { return actualXC->getThreadNum(); }
307
308    bool validInstAddr(Addr addr) { return actualXC->validInstAddr(addr); }
309    bool validDataAddr(Addr addr) { return actualXC->validDataAddr(addr); }
310    int getInstAsid() { return actualXC->getInstAsid(); }
311    int getDataAsid() { return actualXC->getDataAsid(); }
312
313    Fault translateInstReq(MemReqPtr &req)
314    { return actualXC->translateInstReq(req); }
315
316    Fault translateDataReadReq(MemReqPtr &req)
317    { return actualXC->translateDataReadReq(req); }
318
319    Fault translateDataWriteReq(MemReqPtr &req)
320    { return actualXC->translateDataWriteReq(req); }
321
322    // @todo: Do I need this?
323    MachInst getInst() { return actualXC->getInst(); }
324
325    // @todo: Do I need this?
326    void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
327
328    void clearArchRegs() { actualXC->clearArchRegs(); }
329
330    //
331    // New accessors for new decoder.
332    //
333    uint64_t readIntReg(int reg_idx)
334    { return actualXC->readIntReg(reg_idx); }
335
336    float readFloatRegSingle(int reg_idx)
337    { return actualXC->readFloatRegSingle(reg_idx); }
338
339    double readFloatRegDouble(int reg_idx)
340    { return actualXC->readFloatRegDouble(reg_idx); }
341
342    uint64_t readFloatRegInt(int reg_idx)
343    { return actualXC->readFloatRegInt(reg_idx); }
344
345    void setIntReg(int reg_idx, uint64_t val)
346    { actualXC->setIntReg(reg_idx, val); }
347
348    void setFloatRegSingle(int reg_idx, float val)
349    { actualXC->setFloatRegSingle(reg_idx, val); }
350
351    void setFloatRegDouble(int reg_idx, double val)
352    { actualXC->setFloatRegDouble(reg_idx, val); }
353
354    void setFloatRegInt(int reg_idx, uint64_t val)
355    { actualXC->setFloatRegInt(reg_idx, val); }
356
357    uint64_t readPC() { return actualXC->readPC(); }
358
359    void setPC(uint64_t val) { actualXC->setPC(val); }
360
361    uint64_t readNextPC() { return actualXC->readNextPC(); }
362
363    void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
364
365    MiscReg readMiscReg(int misc_reg)
366    { return actualXC->readMiscReg(misc_reg); }
367
368    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
369    { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
370
371    Fault setMiscReg(int misc_reg, const MiscReg &val)
372    { return actualXC->setMiscReg(misc_reg, val); }
373
374    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
375    { return actualXC->setMiscRegWithEffect(misc_reg, val); }
376
377    unsigned readStCondFailures()
378    { return actualXC->readStCondFailures(); }
379
380    void setStCondFailures(unsigned sc_failures)
381    { actualXC->setStCondFailures(sc_failures); }
382
383#if FULL_SYSTEM
384    int readIntrFlag() { return actualXC->readIntrFlag(); }
385
386    void setIntrFlag(int val) { actualXC->setIntrFlag(val); }
387
388    Fault hwrei() { return actualXC->hwrei(); }
389
390    bool inPalMode() { return actualXC->inPalMode(); }
391
392    bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
393#endif
394
395    // @todo: Fix this!
396    bool misspeculating() { return actualXC->misspeculating(); }
397
398#if !FULL_SYSTEM
399    IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
400
401    // used to shift args for indirect syscall
402    void setSyscallArg(int i, IntReg val)
403    { actualXC->setSyscallArg(i, val); }
404
405    void setSyscallReturn(SyscallReturn return_value)
406    { actualXC->setSyscallReturn(return_value); }
407
408    void syscall() { actualXC->syscall(); }
409
410    Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
411
412    void setFuncExeInst(Counter new_val)
413    { return actualXC->setFuncExeInst(new_val); }
414#endif
415};
416
417#endif
418