thread_context.hh revision 1858
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_EXEC_CONTEXT_HH__
30#define __CPU_EXEC_CONTEXT_HH__
31
32#include "config/full_system.hh"
33#include "mem/functional/functional.hh"
34#include "mem/mem_req.hh"
35#include "sim/host.hh"
36#include "sim/serialize.hh"
37#include "targetarch/byte_swap.hh"
38
39// forward declaration: see functional_memory.hh
40class FunctionalMemory;
41class PhysicalMemory;
42class BaseCPU;
43
44#if FULL_SYSTEM
45
46#include "sim/system.hh"
47#include "targetarch/alpha_memory.hh"
48
49class MemoryController;
50class StaticInstBase;
51namespace Kernel { class Binning; class Statistics; }
52
53#else // !FULL_SYSTEM
54
55#include "sim/process.hh"
56
57#endif // FULL_SYSTEM
58
59//
60// The ExecContext object represents a functional context for
61// instruction execution.  It incorporates everything required for
62// architecture-level functional simulation of a single thread.
63//
64
65class ExecContext
66{
67  public:
68    enum Status
69    {
70        /// Initialized but not running yet.  All CPUs start in
71        /// this state, but most transition to Active on cycle 1.
72        /// In MP or SMT systems, non-primary contexts will stay
73        /// in this state until a thread is assigned to them.
74        Unallocated,
75
76        /// Running.  Instructions should be executed only when
77        /// the context is in this state.
78        Active,
79
80        /// Temporarily inactive.  Entered while waiting for
81        /// synchronization, etc.
82        Suspended,
83
84        /// Permanently shut down.  Entered when target executes
85        /// m5exit pseudo-instruction.  When all contexts enter
86        /// this state, the simulation will terminate.
87        Halted
88    };
89
90  private:
91    Status _status;
92
93  public:
94    Status status() const { return _status; }
95
96    /// Set the status to Active.  Optional delay indicates number of
97    /// cycles to wait before beginning execution.
98    void activate(int delay = 1);
99
100    /// Set the status to Suspended.
101    void suspend();
102
103    /// Set the status to Unallocated.
104    void deallocate();
105
106    /// Set the status to Halted.
107    void halt();
108
109  public:
110    RegFile regs;	// correct-path register context
111
112    // pointer to CPU associated with this context
113    BaseCPU *cpu;
114
115    // Current instruction
116    MachInst inst;
117
118    // Index of hardware thread context on the CPU that this represents.
119    int thread_num;
120
121    // ID of this context w.r.t. the System or Process object to which
122    // it belongs.  For full-system mode, this is the system CPU ID.
123    int cpu_id;
124
125#if FULL_SYSTEM
126    FunctionalMemory *mem;
127    AlphaITB *itb;
128    AlphaDTB *dtb;
129    System *system;
130
131    // the following two fields are redundant, since we can always
132    // look them up through the system pointer, but we'll leave them
133    // here for now for convenience
134    MemoryController *memctrl;
135    PhysicalMemory *physmem;
136
137    Kernel::Binning *kernelBinning;
138    Kernel::Statistics *kernelStats;
139    bool bin;
140    bool fnbin;
141    void execute(const StaticInstBase *inst);
142
143#else
144    Process *process;
145
146    FunctionalMemory *mem;	// functional storage for process address space
147
148    // Address space ID.  Note that this is used for TIMING cache
149    // simulation only; all functional memory accesses should use
150    // one of the FunctionalMemory pointers above.
151    short asid;
152
153#endif
154
155    /**
156     * Temporary storage to pass the source address from copy_load to
157     * copy_store.
158     * @todo Remove this temporary when we have a better way to do it.
159     */
160    Addr copySrcAddr;
161    /**
162     * Temp storage for the physical source address of a copy.
163     * @todo Remove this temporary when we have a better way to do it.
164     */
165    Addr copySrcPhysAddr;
166
167
168    /*
169     * number of executed instructions, for matching with syscall trace
170     * points in EIO files.
171     */
172    Counter func_exe_inst;
173
174    //
175    // Count failed store conditionals so we can warn of apparent
176    // application deadlock situations.
177    unsigned storeCondFailures;
178
179    // constructor: initialize context from given process structure
180#if FULL_SYSTEM
181    ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
182                AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
183#else
184    ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
185    ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
186                int _asid);
187#endif
188    virtual ~ExecContext();
189
190    virtual void takeOverFrom(ExecContext *oldContext);
191
192    void regStats(const std::string &name);
193
194    void serialize(std::ostream &os);
195    void unserialize(Checkpoint *cp, const std::string &section);
196
197#if FULL_SYSTEM
198    bool validInstAddr(Addr addr) { return true; }
199    bool validDataAddr(Addr addr) { return true; }
200    int getInstAsid() { return regs.instAsid(); }
201    int getDataAsid() { return regs.dataAsid(); }
202
203    Fault translateInstReq(MemReqPtr &req)
204    {
205        return itb->translate(req);
206    }
207
208    Fault translateDataReadReq(MemReqPtr &req)
209    {
210        return dtb->translate(req, false);
211    }
212
213    Fault translateDataWriteReq(MemReqPtr &req)
214    {
215        return dtb->translate(req, true);
216    }
217
218#else
219    bool validInstAddr(Addr addr)
220    { return process->validInstAddr(addr); }
221
222    bool validDataAddr(Addr addr)
223    { return process->validDataAddr(addr); }
224
225    int getInstAsid() { return asid; }
226    int getDataAsid() { return asid; }
227
228    Fault dummyTranslation(MemReqPtr &req)
229    {
230#if 0
231        assert((req->vaddr >> 48 & 0xffff) == 0);
232#endif
233
234        // put the asid in the upper 16 bits of the paddr
235        req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
236        req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
237        return No_Fault;
238    }
239    Fault translateInstReq(MemReqPtr &req)
240    {
241        return dummyTranslation(req);
242    }
243    Fault translateDataReadReq(MemReqPtr &req)
244    {
245        return dummyTranslation(req);
246    }
247    Fault translateDataWriteReq(MemReqPtr &req)
248    {
249        return dummyTranslation(req);
250    }
251
252#endif
253
254    template <class T>
255    Fault read(MemReqPtr &req, T &data)
256    {
257#if FULL_SYSTEM && defined(TARGET_ALPHA)
258        if (req->flags & LOCKED) {
259            MiscRegFile *cregs = &req->xc->regs.miscRegs;
260            cregs->lock_addr = req->paddr;
261            cregs->lock_flag = true;
262        }
263#endif
264
265        Fault error;
266        error = mem->read(req, data);
267        data = gtoh(data);
268        return error;
269    }
270
271    template <class T>
272    Fault write(MemReqPtr &req, T &data)
273    {
274#if FULL_SYSTEM && defined(TARGET_ALPHA)
275
276        MiscRegFile *cregs;
277
278        // If this is a store conditional, act appropriately
279        if (req->flags & LOCKED) {
280            cregs = &req->xc->regs.miscRegs;
281
282            if (req->flags & UNCACHEABLE) {
283                // Don't update result register (see stq_c in isa_desc)
284                req->result = 2;
285                req->xc->storeCondFailures = 0;//Needed? [RGD]
286            } else {
287                req->result = cregs->lock_flag;
288                if (!cregs->lock_flag ||
289                    ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
290                    cregs->lock_flag = false;
291                    if (((++req->xc->storeCondFailures) % 100000) == 0) {
292                        std::cerr << "Warning: "
293                                  << req->xc->storeCondFailures
294                                  << " consecutive store conditional failures "
295                                  << "on cpu " << req->xc->cpu_id
296                                  << std::endl;
297                    }
298                    return No_Fault;
299                }
300                else req->xc->storeCondFailures = 0;
301            }
302        }
303
304        // Need to clear any locked flags on other proccessors for
305        // this address.  Only do this for succsful Store Conditionals
306        // and all other stores (WH64?).  Unsuccessful Store
307        // Conditionals would have returned above, and wouldn't fall
308        // through.
309        for (int i = 0; i < system->execContexts.size(); i++){
310            cregs = &system->execContexts[i]->regs.miscRegs;
311            if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
312                cregs->lock_flag = false;
313            }
314        }
315
316#endif
317        return mem->write(req, (T)htog(data));
318    }
319
320    virtual bool misspeculating();
321
322
323    MachInst getInst() { return inst; }
324
325    void setInst(MachInst new_inst)
326    {
327        inst = new_inst;
328    }
329
330    Fault instRead(MemReqPtr &req)
331    {
332        return mem->read(req, inst);
333    }
334
335    //
336    // New accessors for new decoder.
337    //
338    uint64_t readIntReg(int reg_idx)
339    {
340        return regs.intRegFile[reg_idx];
341    }
342
343    float readFloatRegSingle(int reg_idx)
344    {
345        return (float)regs.floatRegFile.d[reg_idx];
346    }
347
348    double readFloatRegDouble(int reg_idx)
349    {
350        return regs.floatRegFile.d[reg_idx];
351    }
352
353    uint64_t readFloatRegInt(int reg_idx)
354    {
355        return regs.floatRegFile.q[reg_idx];
356    }
357
358    void setIntReg(int reg_idx, uint64_t val)
359    {
360        regs.intRegFile[reg_idx] = val;
361    }
362
363    void setFloatRegSingle(int reg_idx, float val)
364    {
365        regs.floatRegFile.d[reg_idx] = (double)val;
366    }
367
368    void setFloatRegDouble(int reg_idx, double val)
369    {
370        regs.floatRegFile.d[reg_idx] = val;
371    }
372
373    void setFloatRegInt(int reg_idx, uint64_t val)
374    {
375        regs.floatRegFile.q[reg_idx] = val;
376    }
377
378    uint64_t readPC()
379    {
380        return regs.pc;
381    }
382
383    void setNextPC(uint64_t val)
384    {
385        regs.npc = val;
386    }
387
388    uint64_t readUniq()
389    {
390        return regs.miscRegs.uniq;
391    }
392
393    void setUniq(uint64_t val)
394    {
395        regs.miscRegs.uniq = val;
396    }
397
398    uint64_t readFpcr()
399    {
400        return regs.miscRegs.fpcr;
401    }
402
403    void setFpcr(uint64_t val)
404    {
405        regs.miscRegs.fpcr = val;
406    }
407
408#if FULL_SYSTEM
409    uint64_t readIpr(int idx, Fault &fault);
410    Fault setIpr(int idx, uint64_t val);
411    int readIntrFlag() { return regs.intrflag; }
412    void setIntrFlag(int val) { regs.intrflag = val; }
413    Fault hwrei();
414    bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
415    void ev5_trap(Fault fault);
416    bool simPalCheck(int palFunc);
417#endif
418
419    /** Meant to be more generic trap function to be
420     *  called when an instruction faults.
421     *  @param fault The fault generated by executing the instruction.
422     *  @todo How to do this properly so it's dependent upon ISA only?
423     */
424
425    void trap(Fault fault);
426
427#if !FULL_SYSTEM
428    IntReg getSyscallArg(int i)
429    {
430        return regs.intRegFile[ArgumentReg0 + i];
431    }
432
433    // used to shift args for indirect syscall
434    void setSyscallArg(int i, IntReg val)
435    {
436        regs.intRegFile[ArgumentReg0 + i] = val;
437    }
438
439    void setSyscallReturn(SyscallReturn return_value)
440    {
441        // check for error condition.  Alpha syscall convention is to
442        // indicate success/failure in reg a3 (r19) and put the
443        // return value itself in the standard return value reg (v0).
444        const int RegA3 = 19;	// only place this is used
445        if (return_value.successful()) {
446            // no error
447            regs.intRegFile[RegA3] = 0;
448            regs.intRegFile[ReturnValueReg] = return_value.value();
449        } else {
450            // got an error, return details
451            regs.intRegFile[RegA3] = (IntReg) -1;
452            regs.intRegFile[ReturnValueReg] = -return_value.value();
453        }
454    }
455
456    void syscall()
457    {
458        process->syscall(this);
459    }
460#endif
461};
462
463
464// for non-speculative execution context, spec_mode is always false
465inline bool
466ExecContext::misspeculating()
467{
468    return false;
469}
470
471#endif // __CPU_EXEC_CONTEXT_HH__
472