thread_context.hh revision 12406
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2012, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5412104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 609020Sgblack@eecs.umich.edu class Decoder; 613453Sgblack@eecs.umich.edu} 622190SN/Aclass BaseCPU; 6312406Sgabeblack@google.comclass BaseTLB; 648887Sgeoffrey.blake@arm.comclass CheckerCPU; 657680Sgblack@eecs.umich.educlass Checkpoint; 662313SN/Aclass EndQuiesceEvent; 678706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 688706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 698706Sandreas.hansson@arm.comclass PortProxy; 702190SN/Aclass Process; 712190SN/Aclass System; 723548Sgblack@eecs.umich.edunamespace TheISA { 733548Sgblack@eecs.umich.edu namespace Kernel { 743548Sgblack@eecs.umich.edu class Statistics; 758902Sandreas.hansson@arm.com } 768902Sandreas.hansson@arm.com} 772SN/A 782680Sktlim@umich.edu/** 792680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 802680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 812680Sktlim@umich.edu * state that might be needed by external objects, ranging from 822680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 832680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 842680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 852680Sktlim@umich.edu * 862680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 872680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 882680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 892682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 902680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 912680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 922680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 932680Sktlim@umich.edu */ 942680Sktlim@umich.educlass ThreadContext 952SN/A{ 962107SN/A protected: 972107SN/A typedef TheISA::MachInst MachInst; 982190SN/A typedef TheISA::IntReg IntReg; 992455SN/A typedef TheISA::FloatReg FloatReg; 1002455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1019920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 1022159SN/A typedef TheISA::MiscReg MiscReg; 10312109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10412109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 1052SN/A public: 1066029Ssteve.reinhardt@amd.com 107246SN/A enum Status 108246SN/A { 109246SN/A /// Running. Instructions should be executed only when 110246SN/A /// the context is in this state. 111246SN/A Active, 112246SN/A 113246SN/A /// Temporarily inactive. Entered while waiting for 1142190SN/A /// synchronization, etc. 115246SN/A Suspended, 116246SN/A 117246SN/A /// Permanently shut down. Entered when target executes 118246SN/A /// m5exit pseudo-instruction. When all contexts enter 119246SN/A /// this state, the simulation will terminate. 120246SN/A Halted 121246SN/A }; 1222SN/A 1232680Sktlim@umich.edu virtual ~ThreadContext() { }; 1242423SN/A 1252190SN/A virtual BaseCPU *getCpuPtr() = 0; 126180SN/A 12710110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1282190SN/A 12910190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 13010190Sakash.bagdia@arm.com 13110110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1325715Shsul@eecs.umich.edu 1335715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1345714Shsul@eecs.umich.edu 13510110Sandreas.hansson@arm.com virtual int contextId() const = 0; 1365714Shsul@eecs.umich.edu 1375714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1385714Shsul@eecs.umich.edu 13912406Sgabeblack@google.com virtual BaseTLB *getITBPtr() = 0; 1402190SN/A 14112406Sgabeblack@google.com virtual BaseTLB *getDTBPtr() = 0; 1422521SN/A 1438887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1448733Sgeoffrey.blake@arm.com 1459020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1468541Sgblack@eecs.umich.edu 1474997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1484997Sgblack@eecs.umich.edu 1493548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1502654SN/A 1518852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1522521SN/A 1538852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1543673Srdreslin@umich.edu 1558706Sandreas.hansson@arm.com /** 1568706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1578706Sandreas.hansson@arm.com * the data port of the CPU. 1588706Sandreas.hansson@arm.com * 1598706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1608706Sandreas.hansson@arm.com */ 1618706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1628799Sgblack@eecs.umich.edu 1638852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1642518SN/A 1652190SN/A virtual Process *getProcessPtr() = 0; 1662190SN/A 16711886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) = 0; 16811886Sbrandon.potter@amd.com 1692190SN/A virtual Status status() const = 0; 1702159SN/A 1712235SN/A virtual void setStatus(Status new_status) = 0; 1722103SN/A 17310407Smitch.hayenga@arm.com /// Set the status to Active. 17410407Smitch.hayenga@arm.com virtual void activate() = 0; 175393SN/A 176393SN/A /// Set the status to Suspended. 17710407Smitch.hayenga@arm.com virtual void suspend() = 0; 178393SN/A 179393SN/A /// Set the status to Halted. 18010407Smitch.hayenga@arm.com virtual void halt() = 0; 1812159SN/A 18211627Smichael.lebeane@amd.com /// Quiesce thread context 18311627Smichael.lebeane@amd.com void quiesce(); 18411627Smichael.lebeane@amd.com 18511627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 18611627Smichael.lebeane@amd.com void quiesceTick(Tick resume); 18711627Smichael.lebeane@amd.com 1882190SN/A virtual void dumpFuncProfile() = 0; 1892159SN/A 1902680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1912159SN/A 1922190SN/A virtual void regStats(const std::string &name) = 0; 1932159SN/A 1942313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1952235SN/A 1962235SN/A // Not necessarily the best location for these... 1972235SN/A // Having an extra function just to read these is obnoxious 1982235SN/A virtual Tick readLastActivate() = 0; 1992235SN/A virtual Tick readLastSuspend() = 0; 2002254SN/A 2012254SN/A virtual void profileClear() = 0; 2022254SN/A virtual void profileSample() = 0; 2032235SN/A 2042680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2052159SN/A 2062190SN/A virtual void clearArchRegs() = 0; 2072159SN/A 2082159SN/A // 2092159SN/A // New accessors for new decoder. 2102159SN/A // 2112190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2122159SN/A 2132455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2142159SN/A 2152455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2162159SN/A 21712109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 21812109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22112109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22312109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 22412109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const = 0; 22512109SRekai.GonzalezAlberquilla@arm.com 22612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 22712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 22812109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const = 0; 22912109SRekai.GonzalezAlberquilla@arm.com 23012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 23112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 23212109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const = 0; 23312109SRekai.GonzalezAlberquilla@arm.com 23412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 23512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 23612109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const = 0; 23712109SRekai.GonzalezAlberquilla@arm.com 23812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 23912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) = 0; 24112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) = 0; 24312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) = 0; 24512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) = 0; 24712109SRekai.GonzalezAlberquilla@arm.com /** @} */ 24812109SRekai.GonzalezAlberquilla@arm.com 24912109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElem(const RegId& reg) const = 0; 25012109SRekai.GonzalezAlberquilla@arm.com 2519920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) = 0; 2529920Syasuko.eckert@amd.com 2532190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2542159SN/A 2552455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2562159SN/A 2572455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2582455SN/A 25912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 26012109SRekai.GonzalezAlberquilla@arm.com 26112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 26212109SRekai.GonzalezAlberquilla@arm.com 2639920Syasuko.eckert@amd.com virtual void setCCReg(int reg_idx, CCReg val) = 0; 2649920Syasuko.eckert@amd.com 2657720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2662159SN/A 2677720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2682159SN/A 26911886Sbrandon.potter@amd.com void 27011886Sbrandon.potter@amd.com setNPC(Addr val) 27111886Sbrandon.potter@amd.com { 27211886Sbrandon.potter@amd.com TheISA::PCState pc_state = pcState(); 27311886Sbrandon.potter@amd.com pc_state.setNPC(val); 27411886Sbrandon.potter@amd.com pcState(pc_state); 27511886Sbrandon.potter@amd.com } 27611886Sbrandon.potter@amd.com 2778733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2788733Sgeoffrey.blake@arm.com 2797720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2802159SN/A 2817720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2822159SN/A 2837720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2845260Sksewell@umich.edu 28510698Sandreas.hansson@arm.com virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; 2864172Ssaidi@eecs.umich.edu 2872190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2882159SN/A 2894172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2902190SN/A 2913468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2922190SN/A 29312106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const = 0; 2946313Sgblack@eecs.umich.edu 2956221Snate@binkert.org virtual uint64_t 29612106SRekai.GonzalezAlberquilla@arm.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) 2976221Snate@binkert.org { 2986221Snate@binkert.org return 0; 2996221Snate@binkert.org } 3004661Sksewell@umich.edu 3016221Snate@binkert.org virtual void 30212106SRekai.GonzalezAlberquilla@arm.com setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid) 3036221Snate@binkert.org { 3046221Snate@binkert.org } 3054661Sksewell@umich.edu 3062235SN/A // Also not necessarily the best location for these two. Hopefully will go 3072235SN/A // away once we decide upon where st cond failures goes. 3082190SN/A virtual unsigned readStCondFailures() = 0; 3092190SN/A 3102190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 3112159SN/A 3122235SN/A // Same with st cond failures. 3132190SN/A virtual Counter readFuncExeInst() = 0; 3142834Sksewell@umich.edu 31511877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 3164111Sgblack@eecs.umich.edu 3172834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 3182834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 3192834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 3202834Sksewell@umich.edu virtual int exit() { return 1; }; 3212525SN/A 3225217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 3235217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 3249426SAndreas.Sandberg@ARM.com 3259426SAndreas.Sandberg@ARM.com /** @{ */ 3269426SAndreas.Sandberg@ARM.com /** 3279426SAndreas.Sandberg@ARM.com * Flat register interfaces 3289426SAndreas.Sandberg@ARM.com * 3299426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 3309426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 33112106SRekai.GonzalezAlberquilla@arm.com * flattenRegId()) to map it into the 3329426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 3339426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 3349426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 3359426SAndreas.Sandberg@ARM.com */ 3369426SAndreas.Sandberg@ARM.com 3379426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx) = 0; 3389426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val) = 0; 3399426SAndreas.Sandberg@ARM.com 3409426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx) = 0; 3419426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 3429426SAndreas.Sandberg@ARM.com 3439426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 3449426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 3459426SAndreas.Sandberg@ARM.com 34612109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; 34712109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; 34812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0; 34912109SRekai.GonzalezAlberquilla@arm.com 35012109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElemFlat(const RegIndex& idx, 35112109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIdx) const = 0; 35212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, 35312109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) = 0; 35412109SRekai.GonzalezAlberquilla@arm.com 3559920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx) = 0; 3569920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val) = 0; 3579426SAndreas.Sandberg@ARM.com /** @} */ 3589426SAndreas.Sandberg@ARM.com 3592159SN/A}; 3602159SN/A 3612682Sktlim@umich.edu/** 3622682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 3632682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 3642682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 3652682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 3662682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 3672682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3682682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3692682Sktlim@umich.edu * simple_thread.hh for an example of this. 3702682Sktlim@umich.edu */ 3712680Sktlim@umich.edutemplate <class TC> 3722680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3732190SN/A{ 3742190SN/A public: 3752680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3762680Sktlim@umich.edu { actualTC = actual_tc; } 3772159SN/A 3782190SN/A private: 3792680Sktlim@umich.edu TC *actualTC; 3802SN/A 3812SN/A public: 3822SN/A 3832680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3842SN/A 38510110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 3862SN/A 38710190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 38810190Sakash.bagdia@arm.com 38910110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 3905715Shsul@eecs.umich.edu 39110110Sandreas.hansson@arm.com void setThreadId(int id) { actualTC->setThreadId(id); } 3925714Shsul@eecs.umich.edu 39310110Sandreas.hansson@arm.com int contextId() const { return actualTC->contextId(); } 3945714Shsul@eecs.umich.edu 3955714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3965714Shsul@eecs.umich.edu 39712406Sgabeblack@google.com BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 3981917SN/A 39912406Sgabeblack@google.com BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 4002521SN/A 4018887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 4028733Sgeoffrey.blake@arm.com 4039020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 4048541Sgblack@eecs.umich.edu 4054997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 4064997Sgblack@eecs.umich.edu 4073548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 4083548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 4092654SN/A 4108852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 4112521SN/A 4128852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 4133673Srdreslin@umich.edu 4148706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 4158799Sgblack@eecs.umich.edu 4168852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 4172518SN/A 4182680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 4192SN/A 42011886Sbrandon.potter@amd.com void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 42111886Sbrandon.potter@amd.com 4222680Sktlim@umich.edu Status status() const { return actualTC->status(); } 423595SN/A 4242680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 4252SN/A 42610407Smitch.hayenga@arm.com /// Set the status to Active. 42710407Smitch.hayenga@arm.com void activate() { actualTC->activate(); } 4282SN/A 4292190SN/A /// Set the status to Suspended. 43010407Smitch.hayenga@arm.com void suspend() { actualTC->suspend(); } 4312SN/A 4322190SN/A /// Set the status to Halted. 43310407Smitch.hayenga@arm.com void halt() { actualTC->halt(); } 434217SN/A 43511627Smichael.lebeane@amd.com /// Quiesce thread context 43611627Smichael.lebeane@amd.com void quiesce() { actualTC->quiesce(); } 43711627Smichael.lebeane@amd.com 43811627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 43911627Smichael.lebeane@amd.com void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); } 44011627Smichael.lebeane@amd.com 4412680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 4422190SN/A 4432680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 4442680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 4452190SN/A 4462680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 4472190SN/A 4482680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 4492235SN/A 4502680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 4512680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 4522254SN/A 4532680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 4542680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 4552SN/A 4562190SN/A // @todo: Do I need this? 4572680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 4582SN/A 4592680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 460716SN/A 4612SN/A // 4622SN/A // New accessors for new decoder. 4632SN/A // 4642SN/A uint64_t readIntReg(int reg_idx) 4652680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 4662SN/A 4672455SN/A FloatReg readFloatReg(int reg_idx) 4682680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 4692SN/A 4702455SN/A FloatRegBits readFloatRegBits(int reg_idx) 4712680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4722SN/A 47312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(const RegId& reg) const 47412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecReg(reg); } 47512109SRekai.GonzalezAlberquilla@arm.com 47612109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(const RegId& reg) 47712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecReg(reg); } 47812109SRekai.GonzalezAlberquilla@arm.com 47912109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 48012109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 48112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 48212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 48312109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 48412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec8BitLaneReg(reg); } 48512109SRekai.GonzalezAlberquilla@arm.com 48612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 48712109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 48812109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 48912109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec16BitLaneReg(reg); } 49012109SRekai.GonzalezAlberquilla@arm.com 49112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 49212109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 49312109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 49412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec32BitLaneReg(reg); } 49512109SRekai.GonzalezAlberquilla@arm.com 49612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 49712109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 49812109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 49912109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec64BitLaneReg(reg); } 50012109SRekai.GonzalezAlberquilla@arm.com 50112109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 50212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 50312109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 50412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 50512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 50612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 50712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 50812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 50912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 51012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 51112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 51212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 51312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 51412109SRekai.GonzalezAlberquilla@arm.com /** @} */ 51512109SRekai.GonzalezAlberquilla@arm.com 51612109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 51712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElem(reg); } 51812109SRekai.GonzalezAlberquilla@arm.com 5199920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 5209920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 5219920Syasuko.eckert@amd.com 5222SN/A void setIntReg(int reg_idx, uint64_t val) 5232680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 5242SN/A 5252455SN/A void setFloatReg(int reg_idx, FloatReg val) 5262680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 5272SN/A 5282455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 5292680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 5302SN/A 53112109SRekai.GonzalezAlberquilla@arm.com void setVecReg(const RegId& reg, const VecRegContainer& val) 53212109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecReg(reg, val); } 53312109SRekai.GonzalezAlberquilla@arm.com 53412109SRekai.GonzalezAlberquilla@arm.com void setVecElem(const RegId& reg, const VecElem& val) 53512109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElem(reg, val); } 53612109SRekai.GonzalezAlberquilla@arm.com 5379920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 5389920Syasuko.eckert@amd.com { actualTC->setCCReg(reg_idx, val); } 5399920Syasuko.eckert@amd.com 5407720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 5412SN/A 5427720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 5432206SN/A 5448733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 5458733Sgeoffrey.blake@arm.com 5467720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 5477720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 5487720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 5495260Sksewell@umich.edu 5507597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 5517597Sminkyu.jeong@arm.com 5527597Sminkyu.jeong@arm.com void setPredicate(bool val) 5537597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 5547597Sminkyu.jeong@arm.com 55510698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 5564172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 5574172Ssaidi@eecs.umich.edu 5582159SN/A MiscReg readMiscReg(int misc_reg) 5592680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 5602SN/A 5614172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 5624172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 5632SN/A 5643468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 5652680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 5662SN/A 56712106SRekai.GonzalezAlberquilla@arm.com RegId flattenRegId(const RegId& regId) const 56812106SRekai.GonzalezAlberquilla@arm.com { return actualTC->flattenRegId(regId); } 56910033SAli.Saidi@ARM.com 5702190SN/A unsigned readStCondFailures() 5712680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 5722190SN/A 5732190SN/A void setStCondFailures(unsigned sc_failures) 5742680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 5752SN/A 57611877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 57711877Sbrandon.potter@amd.com { actualTC->syscall(callnum, fault); } 5784111Sgblack@eecs.umich.edu 5792680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 5809426SAndreas.Sandberg@ARM.com 5819426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 5829426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 5839426SAndreas.Sandberg@ARM.com 5849426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 5859426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 5869426SAndreas.Sandberg@ARM.com 5879426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 5889426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 5899426SAndreas.Sandberg@ARM.com 5909426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 5919426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 5929426SAndreas.Sandberg@ARM.com 5939426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 5949426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 5959426SAndreas.Sandberg@ARM.com 5969426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 5979426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 5989920Syasuko.eckert@amd.com 59912109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegFlat(int id) const 60012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecRegFlat(id); } 60112109SRekai.GonzalezAlberquilla@arm.com 60212109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegFlat(int id) 60312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecRegFlat(id); } 60412109SRekai.GonzalezAlberquilla@arm.com 60512109SRekai.GonzalezAlberquilla@arm.com void setVecRegFlat(int idx, const VecRegContainer& val) 60612109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecRegFlat(idx, val); } 60712109SRekai.GonzalezAlberquilla@arm.com 60812109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& id, 60912109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 61012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElemFlat(id, elemIndex); } 61112109SRekai.GonzalezAlberquilla@arm.com 61212109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex, 61312109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) 61412109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElemFlat(id, elemIndex, val); } 61512109SRekai.GonzalezAlberquilla@arm.com 6169920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 6179920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 6189920Syasuko.eckert@amd.com 6199920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 6209920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 6212SN/A}; 6222SN/A 6239428SAndreas.Sandberg@ARM.com/** @{ */ 6249428SAndreas.Sandberg@ARM.com/** 6259428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 6269428SAndreas.Sandberg@ARM.com * 6279428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 6289428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 6299428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 6309428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 6319428SAndreas.Sandberg@ARM.com */ 6329428SAndreas.Sandberg@ARM.com 63310905Sandreas.sandberg@arm.comvoid serialize(ThreadContext &tc, CheckpointOut &cp); 63410905Sandreas.sandberg@arm.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 6359428SAndreas.Sandberg@ARM.com 6369428SAndreas.Sandberg@ARM.com/** @} */ 6379428SAndreas.Sandberg@ARM.com 6389441SAndreas.Sandberg@ARM.com 6399441SAndreas.Sandberg@ARM.com/** 6409441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 6419441SAndreas.Sandberg@ARM.com * 6429441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 6439441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 6449441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 6459441SAndreas.Sandberg@ARM.com * 6469441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 6479441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 6489441SAndreas.Sandberg@ARM.com */ 6499441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 6509441SAndreas.Sandberg@ARM.com 6512190SN/A#endif 652